Update to the LLVM 4.0 release branch

2017-04-03 14:42:55 +03:00
1 parent 423f5a656a
commit 2504fdbd88
@@ -14,15 +14,15 @@ RUN git config --global user.name "VideoLAN Buildbot" && \
 WORKDIR /build
-RUN git clone -b release_39 --depth=1 https://github.com/llvm-mirror/llvm.git
+RUN git clone -b release_40 --depth=1 https://github.com/llvm-mirror/llvm.git
 RUN cd llvm/tools && \
-    git clone -b release_39 --depth=1 https://github.com/llvm-mirror/clang.git && \
+    git clone -b release_40 --depth=1 https://github.com/llvm-mirror/clang.git && \
-    git clone -b release_39 --depth=1 https://github.com/llvm-mirror/lld.git
+    git clone -b release_40 --depth=1 https://github.com/llvm-mirror/lld.git
 #RUN cd llvm/projects && \
-#    git clone -b release_39 --depth=1 https://github.com/llvm-mirror/libcxx.git && \
+#    git clone -b release_40 --depth=1 https://github.com/llvm-mirror/libcxx.git && \
-#    git clone -b release_39 --depth=1 https://github.com/llvm-mirror/libcxxabi.git && \
+#    git clone -b release_40 --depth=1 https://github.com/llvm-mirror/libcxxabi.git && \
-#    git clone https://github.com/llvm-mirror/libunwind.git -b release_39 --depth=1
+#    git clone https://github.com/llvm-mirror/libunwind.git -b release_40 --depth=1
 RUN mkdir /build/patches
@@ -104,7 +104,7 @@ RUN cd mingw-w64/mingw-w64-crt && \
 RUN cp /build/mingw-w64/mingw-w64-libraries/winpthreads/include/* $MINGW_PREFIX/include/
-RUN git clone -b master --depth=1 https://github.com/llvm-mirror/compiler-rt.git
+RUN git clone -b release_40 --depth=1 https://github.com/llvm-mirror/compiler-rt.git
 # Manually build compiler-rt as a standalone project
 RUN cd compiler-rt && mkdir build && cd build && cmake \
@@ -119,8 +119,8 @@ RUN cd compiler-rt && mkdir build && cd build && cmake \
    -DCMAKE_SIZEOF_VOID_P=4 \
    ../lib/builtins && \
    make -j4 && \
-    mkdir -p /build/prefix/lib/clang/3.9.1/lib/windows && \
+    mkdir -p /build/prefix/lib/clang/4.0.1/lib/windows && \
-    cp lib/windows/libclang_rt.builtins-arm.a /build/prefix/lib/clang/3.9.1/lib/windows
+    cp lib/windows/libclang_rt.builtins-arm.a /build/prefix/lib/clang/4.0.1/lib/windows
 RUN cd mingw-w64/mingw-w64-libraries && cd winstorecompat && \
    autoreconf -vif && \
@@ -134,9 +134,9 @@ RUN cd /build/mingw-w64/mingw-w64-tools/widl && \
    make -j4 && \
    make install 
-RUN git clone -b release_39 --depth=1 https://github.com/llvm-mirror/libcxx.git && \
+RUN git clone -b release_40 --depth=1 https://github.com/llvm-mirror/libcxx.git && \
-    git clone -b release_39 --depth=1 https://github.com/llvm-mirror/libcxxabi.git && \
+    git clone -b release_40 --depth=1 https://github.com/llvm-mirror/libcxxabi.git && \
-    git clone -b release_39 --depth=1 https://github.com/llvm-mirror/libunwind.git
+    git clone -b release_40 --depth=1 https://github.com/llvm-mirror/libunwind.git
 COPY patches/libcxx-*.patch /build/patches/
 RUN cd libcxx && \
@@ -152,7 +152,7 @@ RUN cd libcxxabi && \
 RUN cd libunwind && mkdir build && cd build && \
    CXXFLAGS="-nodefaultlibs -D_LIBUNWIND_IS_BAREMETAL" \
-    LDFLAGS="/build/prefix/armv7-w64-mingw32/lib/crt2.o /build/prefix/armv7-w64-mingw32/lib/crtbegin.o -lmingw32 /build/prefix/bin/../lib/clang/3.9.1/lib/windows/libclang_rt.builtins-arm.a -lmoldname -lmingwex -lmsvcrt -ladvapi32 -lshell32 -luser32 -lkernel32 /build/prefix/armv7-w64-mingw32/lib/crtend.o" \
+    LDFLAGS="/build/prefix/armv7-w64-mingw32/lib/crt2.o /build/prefix/armv7-w64-mingw32/lib/crtbegin.o -lmingw32 /build/prefix/bin/../lib/clang/4.0.1/lib/windows/libclang_rt.builtins-arm.a -lmoldname -lmingwex -lmsvcrt -ladvapi32 -lshell32 -luser32 -lkernel32 /build/prefix/armv7-w64-mingw32/lib/crtend.o" \
    cmake \
        -DCMAKE_CXX_COMPILER_WORKS=TRUE \
        -DLLVM_ENABLE_LIBCXX=TRUE \
@@ -1,7 +1,7 @@
-From 5d2a7cb021208fd23b8b57034d11fef3900397c4 Mon Sep 17 00:00:00 2001
+From 82a145503d9b1aecf8cf45bd7b536543f3342345 Mon Sep 17 00:00:00 2001
 From: Martell Malone <martellmalone@gmail.com>
 Date: Wed, 16 Dec 2015 02:07:06 -0800
-Subject: [PATCH 1/6] mingw-w64: setup new defaults for target
+Subject: [PATCH 1/4] mingw-w64: setup new defaults for target
 runtime: compiler-rt
 c++ lib: libc++
@@ -12,12 +12,12 @@ linker: lld
 2 files changed, 10 insertions(+), 1 deletion(-)
 diff --git a/lib/Driver/ToolChains.h b/lib/Driver/ToolChains.h
-index 4e5c3f7..4de35d6 100644
+index 3240357..3be7f25 100644
 --- a/lib/Driver/ToolChains.h
 +++ b/lib/Driver/ToolChains.h
-@@ -680,6 +680,15 @@ public:
+@@ -714,6 +714,15 @@ public:
-       const llvm::opt::ArgList &DriverArgs,
+ 
-       llvm::opt::ArgStringList &CC1Args) const override;
+   void printVerboseInfo(raw_ostream &OS) const override;
 +  RuntimeLibType GetDefaultRuntimeLibType() const override {
 +    return RuntimeLibType::RLT_CompilerRT;
@@ -32,10 +32,10 @@ index 4e5c3f7..4de35d6 100644
   Tool *getTool(Action::ActionClass AC) const override;
   Tool *buildLinker() const override;
 diff --git a/lib/Driver/Tools.cpp b/lib/Driver/Tools.cpp
-index 95f2850..3fff6d2 100644
+index 3c3d453..2a9a09d 100644
 --- a/lib/Driver/Tools.cpp
 +++ b/lib/Driver/Tools.cpp
-@@ -10376,7 +10376,7 @@ void MinGW::Linker::ConstructJob(Compilation &C, const JobAction &JA,
+@@ -11216,7 +11216,7 @@ void MinGW::Linker::ConstructJob(Compilation &C, const JobAction &JA,
   // handled somewhere else.
   Args.ClaimAllArgs(options::OPT_w);
@@ -1,4 +1,4 @@
-From 4139cf38b1a16aa49a7b9eed79b0cccec1a70ec8 Mon Sep 17 00:00:00 2001
+From 553e9229258fd4127e35ad983217b7e4825fdfef Mon Sep 17 00:00:00 2001
 From: =?UTF-8?q?Hugo=20Beauz=C3=A9e-Luyssen?= <hugo@beauzee.fr>
 Date: Mon, 2 May 2016 15:58:31 +0200
 Subject: [PATCH 2/4] Manually revert 0e2452f3055e2e2cad06a55c5ca9c2be13404781
@@ -9,11 +9,11 @@ This re-enables mingw detection
 1 file changed, 4 insertions(+), 10 deletions(-)
 diff --git a/lib/Driver/MinGWToolChain.cpp b/lib/Driver/MinGWToolChain.cpp
-index 938440b..a1dc25b 100644
+index e971869..1ac3bd3 100644
 --- a/lib/Driver/MinGWToolChain.cpp
 +++ b/lib/Driver/MinGWToolChain.cpp
-@@ -66,23 +66,17 @@ MinGW::MinGW(const Driver &D, const llvm::Triple &Triple, const ArgList &Args)
+@@ -64,23 +64,17 @@ MinGW::MinGW(const Driver &D, const llvm::Triple &Triple, const ArgList &Args)
-     : ToolChain(D, Triple, Args) {
+     : ToolChain(D, Triple, Args), CudaInstallation(D, Triple, Args) {
   getProgramPaths().push_back(getDriver().getInstalledDir());
 -// In Windows there aren't any standard install locations, we search
@@ -1,48 +0,0 @@
 From 80b3c6d7fd1cd993de4454e869fadbae8a456ac1 Mon Sep 17 00:00:00 2001
 From: Renato Golin <renato.golin@linaro.org>
 Date: Wed, 27 Jul 2016 14:12:20 +0000
 Subject: [PATCH 3/4] [ARM] Pass thumb as architecture to the underlying tools,
 when targeting windows
 MIME-Version: 1.0
 Content-Type: text/plain; charset=UTF-8
 Content-Transfer-Encoding: 8bit
 This makes sure that the thumb section flag gets set by the assembler.
 Patch by Martin Storsjö.
 Cherry-picked from SVN trunk commit 276869, git mirror commit
 3f38d952361bac.
 ---
 lib/Driver/ToolChain.cpp    | 4 +++-
 test/Driver/windows-thumb.s | 2 ++
 2 files changed, 5 insertions(+), 1 deletion(-)
 create mode 100644 test/Driver/windows-thumb.s
 diff --git a/lib/Driver/ToolChain.cpp b/lib/Driver/ToolChain.cpp
 index e96688c..d586350 100644
 --- a/lib/Driver/ToolChain.cpp
 +++ b/lib/Driver/ToolChain.cpp
@@ -487,8 +487,10 @@ std::string ToolChain::ComputeLLVMTriple(const ArgList &Args,
       ArchName = "arm";
     // Assembly files should start in ARM mode, unless arch is M-profile.
 +    // Windows is always thumb.
     if ((InputType != types::TY_PP_Asm && Args.hasFlag(options::OPT_mthumb,
 -         options::OPT_mno_thumb, ThumbDefault)) || IsMProfile) {
 +         options::OPT_mno_thumb, ThumbDefault)) || IsMProfile ||
 +         getTriple().isOSWindows()) {
       if (IsBigEndian)
         ArchName = "thumbeb";
       else
 diff --git a/test/Driver/windows-thumb.s b/test/Driver/windows-thumb.s
 new file mode 100644
 index 0000000..afe5b2d
 --- /dev/null
 +++ b/test/Driver/windows-thumb.s
@@ -0,0 +1,2 @@
 +; RUN: %clang -target armv7-windows -c -### %s 2>&1 | FileCheck %s
 +; CHECK: "-triple" "thumbv7-
 -- 
 2.7.4
@@ -1,126 +0,0 @@
 From b9f0418bc4b3f7869d549bb020271c19e69cce26 Mon Sep 17 00:00:00 2001
 From: Saleem Abdulrasool <compnerd@compnerd.org>
 Date: Sat, 6 Aug 2016 17:58:24 +0000
 Subject: [PATCH 4/4] Headers: Add ARM support to intrin.h for MSVC
 compatibility
 MIME-Version: 1.0
 Content-Type: text/plain; charset=UTF-8
 Content-Transfer-Encoding: 8bit
 This fixes compiling with headers from the Windows SDK for ARM, where the
 YieldProcessor function (in winnt.h) refers to _ARM_BARRIER_ISHST.
 The actual MSVC armintr.h contains a lot more definitions, but this is enough to
 build code that uses the Windows SDK but doesn't use ARM intrinsics directly.
 An alternative would to just keep the addition to intrin.h (to include
 armintr.h), but not actually ship armintr.h, instead having clang's intrin.h
 include armintr.h from MSVC's include directory. (That one works fine with
 clang, at least for building code that uses the Windows SDK.)
 Patch by Martin Storsjö!
 Cherry-picked from SVN trunk commit 277928, git mirror commit
 cfc8939a5f1.
 ---
 lib/Headers/CMakeLists.txt |  1 +
 lib/Headers/armintr.h      | 45 +++++++++++++++++++++++++++++++++++++++++++++
 lib/Headers/intrin.h       |  4 ++++
 test/Headers/ms-intrin.cpp |  4 ++++
 4 files changed, 54 insertions(+)
 create mode 100644 lib/Headers/armintr.h
 diff --git a/lib/Headers/CMakeLists.txt b/lib/Headers/CMakeLists.txt
 index 657ef7e..600fece 100644
 --- a/lib/Headers/CMakeLists.txt
 +++ b/lib/Headers/CMakeLists.txt
@@ -3,6 +3,7 @@ set(files
   altivec.h
   ammintrin.h
   arm_acle.h
 +  armintr.h
   avx2intrin.h
   avx512bwintrin.h
   avx512cdintrin.h
 diff --git a/lib/Headers/armintr.h b/lib/Headers/armintr.h
 new file mode 100644
 index 0000000..933afcb
 --- /dev/null
 +++ b/lib/Headers/armintr.h
@@ -0,0 +1,45 @@
 +/*===---- armintr.h - ARM Windows intrinsics -------------------------------===
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a copy
 + * of this software and associated documentation files (the "Software"), to deal
 + * in the Software without restriction, including without limitation the rights
 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 + * copies of the Software, and to permit persons to whom the Software is
 + * furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + *
 + *===-----------------------------------------------------------------------===
 + */
 +
 +/* Only include this if we're compiling for the windows platform. */
 +#ifndef _MSC_VER
 +#include_next <armintr.h>
 +#else
 +
 +#ifndef __ARMINTR_H
 +#define __ARMINTR_H
 +
 +typedef enum
 +{
 +  _ARM_BARRIER_SY    = 0xF,
 +  _ARM_BARRIER_ST    = 0xE,
 +  _ARM_BARRIER_ISH   = 0xB,
 +  _ARM_BARRIER_ISHST = 0xA,
 +  _ARM_BARRIER_NSH   = 0x7,
 +  _ARM_BARRIER_NSHST = 0x6,
 +  _ARM_BARRIER_OSH   = 0x3,
 +  _ARM_BARRIER_OSHST = 0x2
 +} _ARMINTR_BARRIER_TYPE;
 +
 +#endif /* __ARMINTR_H */
 +#endif /* _MSC_VER */
 diff --git a/lib/Headers/intrin.h b/lib/Headers/intrin.h
 index f18711a..268ac4a 100644
 --- a/lib/Headers/intrin.h
 +++ b/lib/Headers/intrin.h
@@ -34,6 +34,10 @@
 #include <x86intrin.h>
 #endif
 +#if defined(__arm__)
 +#include <armintr.h>
 +#endif
 +
 /* For the definition of jmp_buf. */
 #if __STDC_HOSTED__
 #include <setjmp.h>
 diff --git a/test/Headers/ms-intrin.cpp b/test/Headers/ms-intrin.cpp
 index c697428..25c5531 100644
 --- a/test/Headers/ms-intrin.cpp
 +++ b/test/Headers/ms-intrin.cpp
@@ -60,4 +60,8 @@ void f() {
   __readcr3();
   __writecr3(0);
 #endif
 +
 +#ifdef _M_ARM
 +  __dmb(_ARM_BARRIER_ISHST);
 +#endif
 }
 -- 
 2.7.4
@@ -1,17 +1,17 @@
-From c12d174fab12116ed74f3984d12fbff057943f60 Mon Sep 17 00:00:00 2001
+From ebade0c4f7558bb16b2504f06076585d1f618a4c Mon Sep 17 00:00:00 2001
 From: Martell Malone <martellmalone@gmail.com>
 Date: Mon, 15 Aug 2016 20:57:27 -0700
-Subject: [PATCH 5/5] mingw-w64: enable support for __declspec(selectany)
+Subject: [PATCH 3/4] mingw-w64: enable support for __declspec(selectany)
 ---
 include/clang/Basic/Attr.td | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)
 diff --git a/include/clang/Basic/Attr.td b/include/clang/Basic/Attr.td
-index 7da1efe..2d4be9e 100644
+index fa60d51..0739511 100644
 --- a/include/clang/Basic/Attr.td
 +++ b/include/clang/Basic/Attr.td
-@@ -2097,9 +2097,8 @@ def DLLImport : InheritableAttr, TargetSpecificAttr<TargetWindows> {
+@@ -2180,9 +2180,8 @@ def DLLImport : InheritableAttr, TargetSpecificAttr<TargetWindows> {
   let Documentation = [DLLImportDocs];
 }
@@ -1,7 +1,7 @@
-From 33dec3bb0148afe0bcff8c8684833f89c7a61bb6 Mon Sep 17 00:00:00 2001
+From 2488a5d11c8a5ff0c5ab3749dd36ef8ba53bfac1 Mon Sep 17 00:00:00 2001
 From: Martell Malone <martellmalone@gmail.com>
 Date: Fri, 5 Aug 2016 21:50:38 -0700
-Subject: [PATCH 6/6] mingw-w64: support static builds of libc++
+Subject: [PATCH 4/4] mingw-w64: support static builds of libc++
 Static builds require libc++abi to be linked
 Will add support for both modes in future
@@ -11,10 +11,10 @@ Will add support for both modes in future
 2 files changed, 19 insertions(+)
 diff --git a/lib/Driver/MinGWToolChain.cpp b/lib/Driver/MinGWToolChain.cpp
-index a1dc25b..816e11d 100644
+index 1ac3bd3..3c3e319 100644
 --- a/lib/Driver/MinGWToolChain.cpp
 +++ b/lib/Driver/MinGWToolChain.cpp
-@@ -242,3 +242,18 @@ void MinGW::AddClangCXXStdlibIncludeArgs(const ArgList &DriverArgs,
+@@ -249,3 +249,18 @@ void MinGW::AddClangCXXStdlibIncludeArgs(const ArgList &DriverArgs,
     break;
   }
 }
@@ -34,10 +34,10 @@ index a1dc25b..816e11d 100644
 +  }
 +}
 diff --git a/lib/Driver/ToolChains.h b/lib/Driver/ToolChains.h
-index 4de35d6..bfc9b80 100644
+index 3be7f25..f62207d 100644
 --- a/lib/Driver/ToolChains.h
 +++ b/lib/Driver/ToolChains.h
-@@ -676,6 +676,10 @@ public:
+@@ -705,6 +705,10 @@ public:
   void
   AddClangSystemIncludeArgs(const llvm::opt::ArgList &DriverArgs,
                             llvm::opt::ArgStringList &CC1Args) const override;
@@ -1,7 +1,7 @@
-From 808dcadd650fd54174a0c033547a6668bf77e4f1 Mon Sep 17 00:00:00 2001
+From d2b8d30134e620ec5d36be0765e52c7bf9bc57d6 Mon Sep 17 00:00:00 2001
 From: Martell Malone <martellmalone@gmail.com>
 Date: Wed, 28 Oct 2015 19:32:16 +0000
-Subject: [PATCH 1/5] add support for gnu arguments in lld coff
+Subject: [PATCH 1/2] add support for gnu arguments in lld coff
 ---
 COFF/Driver.cpp      | 31 ++++++++++++++++++++++++++++++-
@@ -12,10 +12,10 @@ Subject: [PATCH 1/5] add support for gnu arguments in lld coff
 5 files changed, 75 insertions(+), 2 deletions(-)
 diff --git a/COFF/Driver.cpp b/COFF/Driver.cpp
-index bb6a60e..0821591 100644
+index 4dabd9e..4992296 100644
 --- a/COFF/Driver.cpp
 +++ b/COFF/Driver.cpp
-@@ -125,6 +125,7 @@ void LinkerDriver::parseDirectives(StringRef S) {
+@@ -232,6 +232,7 @@ void LinkerDriver::parseDirectives(StringRef S) {
     case OPT_fastfail:
     case OPT_guardsym:
     case OPT_throwingnew:
@@ -23,7 +23,7 @@ index bb6a60e..0821591 100644
       break;
     default:
       fatal(Arg->getSpelling() + " is not allowed in .drectve");
-@@ -153,6 +154,31 @@ StringRef LinkerDriver::doFindFile(StringRef Filename) {
+@@ -260,6 +261,31 @@ StringRef LinkerDriver::doFindFile(StringRef Filename) {
   return Filename;
 }
@@ -45,7 +45,7 @@ index bb6a60e..0821591 100644
 +      SmallString<128> Path = Dir;
 +      llvm::sys::path::append(Path, Name.c_str());
 +      if (llvm::sys::fs::exists(Path.str()))
-+        return Alloc.save(Path.str());
+        return Saver.save(Path.str());
 +    }
 +  }
 +  fatal("Unable to find library -l" + Filename);
@@ -55,17 +55,17 @@ index bb6a60e..0821591 100644
 // Resolves a file path. This never returns the same path
 // (in that case, it returns None).
 Optional<StringRef> LinkerDriver::findFile(StringRef Filename) {
-@@ -452,6 +478,9 @@ void LinkerDriver::link(llvm::ArrayRef<const char *> ArgsArr) {
+@@ -667,6 +693,9 @@ void LinkerDriver::link(ArrayRef<const char *> ArgsArr) {
-   // for /defaultlib option.
+   for (auto *Arg : Args.filtered(OPT_defaultlib))
-   std::vector<StringRef> Paths;
+     if (Optional<StringRef> Path = findLib(Arg->getValue()))
-   std::vector<MemoryBufferRef> MBs;
+       enqueuePath(*Path);
 +  for (auto *Arg : Args.filtered(OPT_l))
 +    if (Optional<StringRef> Path = searchLibrary(Arg->getValue()))
-+      Paths.push_back(*Path);
+      enqueuePath(*Path);
-   for (auto *Arg : Args.filtered(OPT_INPUT))
+ 
-     if (Optional<StringRef> Path = findFile(Arg->getValue()))
+   // Windows specific -- Create a resource file containing a manifest file.
-       Paths.push_back(*Path);
+   if (Config->Manifest == Configuration::Embed)
-@@ -573,7 +602,7 @@ void LinkerDriver::link(llvm::ArrayRef<const char *> ArgsArr) {
+@@ -753,7 +782,7 @@ void LinkerDriver::link(ArrayRef<const char *> ArgsArr) {
   if (Config->ImageBase == uint64_t(-1))
     Config->ImageBase = getDefaultImageBase();
@@ -75,10 +75,10 @@ index bb6a60e..0821591 100644
     Config->SEHTable = Symtab.addRelative("___safe_se_handler_table", 0);
     Config->SEHCount = Symtab.addAbsolute("___safe_se_handler_count", 0);
 diff --git a/COFF/Driver.h b/COFF/Driver.h
-index 23969ee..230ec35 100644
+index 4489426..d293014 100644
 --- a/COFF/Driver.h
 +++ b/COFF/Driver.h
-@@ -84,6 +84,9 @@ private:
+@@ -86,6 +86,9 @@ private:
   StringRef doFindFile(StringRef Filename);
   StringRef doFindLib(StringRef Filename);
@@ -89,10 +89,10 @@ index 23969ee..230ec35 100644
   void addLibSearchPaths();
 diff --git a/COFF/DriverUtils.cpp b/COFF/DriverUtils.cpp
-index 5d7dc2b..e2f1f2d 100644
+index 14dd004..f5f3d6d 100644
 --- a/COFF/DriverUtils.cpp
 +++ b/COFF/DriverUtils.cpp
-@@ -591,7 +591,7 @@ static const llvm::opt::OptTable::Info infoTable[] = {
+@@ -637,7 +637,7 @@ static const llvm::opt::OptTable::Info infoTable[] = {
 class COFFOptTable : public llvm::opt::OptTable {
 public:
@@ -102,12 +102,12 @@ index 5d7dc2b..e2f1f2d 100644
 // Parses a given list of options.
 diff --git a/COFF/Options.td b/COFF/Options.td
-index e5c9c5b..322b162 100644
+index 9dfbcc8..b3b30a3 100644
 --- a/COFF/Options.td
 +++ b/COFF/Options.td
-@@ -93,6 +93,26 @@ def nosymtab : F<"nosymtab">;
+@@ -99,6 +99,26 @@ def dumppdb : Joined<["/", "-"], "dumppdb">;
- // Flags for debugging
+ def lldmap : F<"lldmap">;
- def lldmap : Joined<["/", "-"], "lldmap:">;
+ def lldmap_file : Joined<["/", "-"], "lldmap:">;
 +
 +def output : Separate<["-"], "o">, Alias<out>;
@@ -133,10 +133,10 @@ index e5c9c5b..322b162 100644
 // The flags below do nothing. They are defined only for link.exe compatibility.
 //==============================================================================
 diff --git a/tools/lld/lld.cpp b/tools/lld/lld.cpp
-index 8805e02..68c8735 100644
+index 0c32ff1..5bd823a 100644
 --- a/tools/lld/lld.cpp
 +++ b/tools/lld/lld.cpp
-@@ -51,6 +51,24 @@ static Flavor getFlavor(StringRef S) {
+@@ -49,6 +49,24 @@ static Flavor getFlavor(StringRef S) {
       .Default(Invalid);
 }
@@ -161,7 +161,7 @@ index 8805e02..68c8735 100644
 static Flavor parseProgname(StringRef Progname) {
 #if __APPLE__
   // Use Darwin driver for "ld" on Darwin.
-@@ -101,6 +119,9 @@ int main(int Argc, const char **Argv) {
+@@ -99,6 +117,9 @@ int main(int Argc, const char **Argv) {
   llvm_shutdown_obj Shutdown;
   std::vector<const char *> Args(Argv, Argv + Argc);
@@ -170,7 +170,7 @@ index 8805e02..68c8735 100644
 +
   switch (parseFlavor(Args)) {
   case Gnu:
-     return !elf::link(Args);
+     return !elf::link(Args, true);
 -- 
 2.7.4
@@ -1,7 +1,7 @@
-From f8cba388440ff846c5f479889fc64a03066ff39c Mon Sep 17 00:00:00 2001
+From 6fa2a85b5bfc696204939659c7f51c185d1d8b47 Mon Sep 17 00:00:00 2001
 From: Martin Storsjo <martin@martin.st>
 Date: Mon, 8 Aug 2016 15:37:59 +0300
-Subject: [PATCH 2/5] Make the "gnu arguments in lld coff" patch not break
+Subject: [PATCH 2/2] Make the "gnu arguments in lld coff" patch not break
 using lld-link in normal MSVC mode
 ---
@@ -11,10 +11,10 @@ Subject: [PATCH 2/5] Make the "gnu arguments in lld coff" patch not break
 3 files changed, 7 insertions(+), 1 deletion(-)
 diff --git a/COFF/Driver.cpp b/COFF/Driver.cpp
-index 0821591..65cfa9f 100644
+index 4992296..b19998f 100644
 --- a/COFF/Driver.cpp
 +++ b/COFF/Driver.cpp
-@@ -602,6 +602,7 @@ void LinkerDriver::link(llvm::ArrayRef<const char *> ArgsArr) {
+@@ -782,6 +782,7 @@ void LinkerDriver::link(ArrayRef<const char *> ArgsArr) {
   if (Config->ImageBase == uint64_t(-1))
     Config->ImageBase = getDefaultImageBase();
@@ -23,10 +23,10 @@ index 0821591..65cfa9f 100644
   if (Config->Machine == I386) {
     Config->SEHTable = Symtab.addRelative("___safe_se_handler_table", 0);
 diff --git a/COFF/DriverUtils.cpp b/COFF/DriverUtils.cpp
-index e2f1f2d..f9c37ec 100644
+index f5f3d6d..aab554f 100644
 --- a/COFF/DriverUtils.cpp
 +++ b/COFF/DriverUtils.cpp
-@@ -591,7 +591,10 @@ static const llvm::opt::OptTable::Info infoTable[] = {
+@@ -637,7 +637,10 @@ static const llvm::opt::OptTable::Info infoTable[] = {
 class COFFOptTable : public llvm::opt::OptTable {
 public:
@@ -39,7 +39,7 @@ index e2f1f2d..f9c37ec 100644
 // Parses a given list of options.
 diff --git a/COFF/Options.td b/COFF/Options.td
-index 322b162..4e7338a 100644
+index b3b30a3..dec6a0a 100644
 --- a/COFF/Options.td
 +++ b/COFF/Options.td
@@ -19,11 +19,13 @@ def align   : P<"align", "Section alignment">;
@@ -1,82 +0,0 @@
 From 2f3ad0343836886143c1f8ac83552c6734e05205 Mon Sep 17 00:00:00 2001
 From: Saleem Abdulrasool <compnerd@compnerd.org>
 Date: Fri, 5 Aug 2016 17:28:21 +0000
 Subject: [PATCH 3/5] COFF ARM: Clear the J1 and J2 bits when applying
 relocations to 24 bit branches
 MIME-Version: 1.0
 Content-Type: text/plain; charset=UTF-8
 Content-Transfer-Encoding: 8bit
 The opcode for the bl branches can initially be F000 F800, i.e.
 the J1 and J2 bits are already set. Therefore mask these bits out
 before or'ing in the new bits.
 Patch by Martin Storsjö!
 Cherry-picked from SVN trunk commit 277836, git mirror commit
 7b7d94e63a.
 ---
 COFF/Chunks.cpp          |  3 ++-
 test/COFF/reloc-arm.test | 13 +++++++++++--
 2 files changed, 13 insertions(+), 3 deletions(-)
 diff --git a/COFF/Chunks.cpp b/COFF/Chunks.cpp
 index 1c1b181..2e6f535 100644
 --- a/COFF/Chunks.cpp
 +++ b/COFF/Chunks.cpp
@@ -103,7 +103,8 @@ static void applyBranch24T(uint8_t *Off, int32_t V) {
   uint32_t J1 = ((~V >> 23) & 1) ^ S;
   uint32_t J2 = ((~V >> 22) & 1) ^ S;
   or16(Off, (S << 10) | ((V >> 12) & 0x3ff));
 -  or16(Off + 2, (J1 << 13) | (J2 << 11) | ((V >> 1) & 0x7ff));
 +  // Clear out the J1 and J2 bits which may be set.
 +  write16le(Off + 2, (read16le(Off + 2) & 0xd000) | (J1 << 13) | (J2 << 11) | ((V >> 1) & 0x7ff));
 }
 void SectionChunk::applyRelARM(uint8_t *Off, uint16_t Type, Defined *Sym,
 diff --git a/test/COFF/reloc-arm.test b/test/COFF/reloc-arm.test
 index 11b863d..f7656e7 100644
 --- a/test/COFF/reloc-arm.test
 +++ b/test/COFF/reloc-arm.test
@@ -9,7 +9,7 @@
 # CHECK: 402030 fe07e62f 00000000 00000000 00000000
 # CHECK: 402040 3e04de2f 00000000 00000000 00000000
 # CHECK: 402050 fe07d62f 00000000 00000000 00000000
 -# CHECK: 402060 00000000 00000000 00000000 00000000
 +# CHECK: 402060 fef0cef7 00000000 00000000 00000000
 --- !COFF
 header:
@@ -23,7 +23,7 @@ sections:
   - Name:            .text
     Characteristics: [ IMAGE_SCN_CNT_CODE, IMAGE_SCN_MEM_PURGEABLE, IMAGE_SCN_MEM_16BIT, IMAGE_SCN_MEM_EXECUTE, IMAGE_SCN_MEM_READ ]
     Alignment:       4096
 -    SectionData:     00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 +    SectionData:     00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f000f8000000000000000000000000
     Relocations:
       - VirtualAddress:  0
         SymbolName:      foo
@@ -43,6 +43,9 @@ sections:
       - VirtualAddress:  80
         SymbolName:      foo
         Type:            21  # IMAGE_REL_AMD64_BLX23T
 +      - VirtualAddress:  96
 +        SymbolName:      bar
 +        Type:            20  # IMAGE_REL_ARM_BRANCH24T
 symbols:
   - Name:            .aaa
     Value:           0
@@ -68,4 +71,10 @@ symbols:
     SimpleType:      IMAGE_SYM_TYPE_NULL
     ComplexType:     IMAGE_SYM_DTYPE_NULL
     StorageClass:    IMAGE_SYM_CLASS_EXTERNAL
 +  - Name:            bar
 +    Value:           0x500000
 +    SectionNumber:   1
 +    SimpleType:      IMAGE_SYM_TYPE_NULL
 +    ComplexType:     IMAGE_SYM_DTYPE_NULL
 +    StorageClass:    IMAGE_SYM_CLASS_EXTERNAL
 ...
 -- 
 2.7.4
@@ -1,64 +0,0 @@
 From 13f5a9ac209dd87b8e3c22151a139954a49a0674 Mon Sep 17 00:00:00 2001
 From: Saleem Abdulrasool <compnerd@compnerd.org>
 Date: Fri, 5 Aug 2016 17:33:24 +0000
 Subject: [PATCH 4/5] COFF ARM: Error out if 24 bit thumb branches are out of
 range
 MIME-Version: 1.0
 Content-Type: text/plain; charset=UTF-8
 Content-Transfer-Encoding: 8bit
 In the ELF linker, the same situation already errors out with "relocation
 R_ARM_THM_CALL out of range".
 Patch by Martin Storsjö!
 Cherry-picked from SVN trunk commit 277838, git mirror commit
 97497d40eee0.
 ---
 COFF/Chunks.cpp                      |  2 ++
 test/COFF/Inputs/far-arm-thumb-abs.s |  2 ++
 test/COFF/arm-thumb-branch-error.s   | 10 ++++++++++
 3 files changed, 14 insertions(+)
 create mode 100644 test/COFF/Inputs/far-arm-thumb-abs.s
 create mode 100644 test/COFF/arm-thumb-branch-error.s
 diff --git a/COFF/Chunks.cpp b/COFF/Chunks.cpp
 index 2e6f535..fb60a8b 100644
 --- a/COFF/Chunks.cpp
 +++ b/COFF/Chunks.cpp
@@ -99,6 +99,8 @@ static void applyBranch20T(uint8_t *Off, int32_t V) {
 }
 static void applyBranch24T(uint8_t *Off, int32_t V) {
 +  if (!isInt<25>(V))
 +    fatal("relocation out of range");
   uint32_t S = V < 0 ? 1 : 0;
   uint32_t J1 = ((~V >> 23) & 1) ^ S;
   uint32_t J2 = ((~V >> 22) & 1) ^ S;
 diff --git a/test/COFF/Inputs/far-arm-thumb-abs.s b/test/COFF/Inputs/far-arm-thumb-abs.s
 new file mode 100644
 index 0000000..9f1b59a
 --- /dev/null
 +++ b/test/COFF/Inputs/far-arm-thumb-abs.s
@@ -0,0 +1,2 @@
 +.global too_far1
 +too_far1 = 0x1401004
 diff --git a/test/COFF/arm-thumb-branch-error.s b/test/COFF/arm-thumb-branch-error.s
 new file mode 100644
 index 0000000..00b835c
 --- /dev/null
 +++ b/test/COFF/arm-thumb-branch-error.s
@@ -0,0 +1,10 @@
 +// RUN: llvm-mc -filetype=obj -triple=thumbv7a-windows-gnu %s -o %t
 +// RUN: llvm-mc -filetype=obj -triple=thumbv7a-windows-gnu %S/Inputs/far-arm-thumb-abs.s -o %tfar
 +// RUN: not lld-link -entry:_start -subsystem:console %t %tfar -out:%t2 2>&1 | FileCheck %s
 +// REQUIRES: arm
 + .syntax unified
 + .globl _start
 +_start:
 + bl  too_far1
 +
 +// CHECK: relocation out of range
 -- 
 2.7.4
@@ -1,77 +0,0 @@
 From c3fa3c7975a537df2e668ea59f074ce5be95b4f5 Mon Sep 17 00:00:00 2001
 From: Saleem Abdulrasool <compnerd@compnerd.org>
 Date: Fri, 5 Aug 2016 18:20:31 +0000
 Subject: [PATCH 5/5] COFF ARM: Apply an existing offset in MOV32T relocations
 MIME-Version: 1.0
 Content-Type: text/plain; charset=UTF-8
 Content-Transfer-Encoding: 8bit
 Don't blindly OR in the new value, but clear the existing one, since it can be
 nonzero. Read out the existing value before, and add into the desired offset.
 (The add is done outside of the applyMOV, to handle potential overflow between
 the two.)
 Patch by Martin Storsjö!
 Cherry-picked from SVN trunk commit 277846, git mirror commit
 3d39965b0cdd0.
 ---
 COFF/Chunks.cpp          | 16 ++++++++++++++--
 test/COFF/reloc-arm.test |  4 ++--
 2 files changed, 16 insertions(+), 4 deletions(-)
 diff --git a/COFF/Chunks.cpp b/COFF/Chunks.cpp
 index fb60a8b..b8d706e 100644
 --- a/COFF/Chunks.cpp
 +++ b/COFF/Chunks.cpp
@@ -81,11 +81,23 @@ void SectionChunk::applyRelX86(uint8_t *Off, uint16_t Type, Defined *Sym,
 }
 static void applyMOV(uint8_t *Off, uint16_t V) {
 -  or16(Off, ((V & 0x800) >> 1) | ((V >> 12) & 0xf));
 -  or16(Off + 2, ((V & 0x700) << 4) | (V & 0xff));
 +  write16le(Off, (read16le(Off) & 0xfbf0) | ((V & 0x800) >> 1) | ((V >> 12) & 0xf));
 +  write16le(Off + 2, (read16le(Off + 2) & 0x8f00) | ((V & 0x700) << 4) | (V & 0xff));
 +}
 +
 +static uint16_t readMOV(uint8_t *Off) {
 +  uint16_t Opcode1 = read16le(Off);
 +  uint16_t Opcode2 = read16le(Off + 2);
 +  uint16_t Imm = (Opcode2 & 0x00ff) | ((Opcode2 >> 4) & 0x0700);
 +  Imm |= ((Opcode1 << 1) & 0x0800) | ((Opcode1 & 0x000f) << 12);
 +  return Imm;
 }
 static void applyMOV32T(uint8_t *Off, uint32_t V) {
 +  uint16_t ImmW = readMOV(Off);     // read MOVW operand
 +  uint16_t ImmT = readMOV(Off + 4); // read MOVT operand
 +  uint32_t Imm = ImmW | (ImmT << 16);
 +  V += Imm;                         // add the immediate offset
   applyMOV(Off, V);           // set MOVW operand
   applyMOV(Off + 4, V >> 16); // set MOVT operand
 }
 diff --git a/test/COFF/reloc-arm.test b/test/COFF/reloc-arm.test
 index f7656e7..b9699e8 100644
 --- a/test/COFF/reloc-arm.test
 +++ b/test/COFF/reloc-arm.test
@@ -5,7 +5,7 @@
 # CHECK: .text:
 # CHECK: 402000 01104000 00000000 00000000 00000000
 # CHECK: 402010 01100000 00000000 00000000 00000000
 -# CHECK: 402020 01000100 00004000 00000000 00000000
 +# CHECK: 402020 41f20009 c0f24009 00000000 00000000
 # CHECK: 402030 fe07e62f 00000000 00000000 00000000
 # CHECK: 402040 3e04de2f 00000000 00000000 00000000
 # CHECK: 402050 fe07d62f 00000000 00000000 00000000
@@ -23,7 +23,7 @@ sections:
   - Name:            .text
     Characteristics: [ IMAGE_SCN_CNT_CODE, IMAGE_SCN_MEM_PURGEABLE, IMAGE_SCN_MEM_16BIT, IMAGE_SCN_MEM_EXECUTE, IMAGE_SCN_MEM_READ ]
     Alignment:       4096
 -    SectionData:     00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f000f8000000000000000000000000
 +    SectionData:     00000000000000000000000000000000000000000000000000000000000000004ff6ff79cff6ff79000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f000f8000000000000000000000000
     Relocations:
       - VirtualAddress:  0
         SymbolName:      foo
 -- 
 2.7.4
@@ -1,613 +0,0 @@
 From 2ff44aa1732a823a77e88bd30219e12cb14a4d66 Mon Sep 17 00:00:00 2001
 From: Sam Parker <sam.parker@arm.com>
 Date: Tue, 19 Jul 2016 14:44:05 +0000
 Subject: [PATCH 1/3] [ARM] Refactor Thumb2 Mul and Mla instr descs
 Recommitting after r274347 was reverted. This patch introduces some
 classes to refactor the 3 and 4 register Thumb2 multiplication
 instruction descriptions, plus improved tests for some of those
 instructions.
 Differential Revision: https://reviews.llvm.org/D21929
 Cherry-picked from SVN trunk commit 275979, git mirror commit
 aa39b5574e.
 ---
 lib/Target/ARM/ARMInstrThumb2.td | 470 ++++++++++++---------------------------
 test/CodeGen/ARM/longMAC.ll      |  30 ++-
 2 files changed, 169 insertions(+), 331 deletions(-)
 diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
 index fe699b2..64f5dad 100644
 --- a/lib/Target/ARM/ARMInstrThumb2.td
 +++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -536,9 +536,9 @@ class T2FourReg<dag oops, dag iops, InstrItinClass itin,
 }
 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
 -                dag oops, dag iops, InstrItinClass itin,
 -                string opc, string asm, list<dag> pattern>
 -  : T2I<oops, iops, itin, opc, asm, pattern> {
 +                string opc, list<dag> pattern>
 +  : T2I<(outs rGPR:$RdLo, rGPR:$RdHi), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
 +         opc, "\t$RdLo, $RdHi, $Rn, $Rm", pattern> {
   bits<4> RdLo;
   bits<4> RdHi;
   bits<4> Rn;
@@ -552,10 +552,11 @@ class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
   let Inst{7-4}   = opc7_4;
   let Inst{3-0}   = Rm;
 }
 -class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4,
 -                dag oops, dag iops, InstrItinClass itin,
 -                string opc, string asm, list<dag> pattern>
 -  : T2I<oops, iops, itin, opc, asm, pattern> {
 +class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4, string opc>
 +  : T2I<(outs rGPR:$RdLo, rGPR:$RdHi),
 +        (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
 +        opc, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
 +        RegConstraint<"$RLo = $RdLo, $RHi = $RdHi"> {
   bits<4> RdLo;
   bits<4> RdHi;
   bits<4> Rn;
@@ -2546,367 +2547,182 @@ def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
   let Inst{7-4} = 0b0000; // Multiply
 }
 -def t2MLA: T2FourReg<
 -                (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
 -                "mla", "\t$Rd, $Rn, $Rm, $Ra",
 -                [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]>,
 -           Requires<[IsThumb2, UseMulOps]> {
 +class T2FourRegMLA<bits<4> op7_4, string opc, list<dag> pattern>
 +  : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
 +               opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
 +               Requires<[IsThumb2, UseMulOps]> {
   let Inst{31-27} = 0b11111;
   let Inst{26-23} = 0b0110;
   let Inst{22-20} = 0b000;
 -  let Inst{7-4} = 0b0000; // Multiply
 +  let Inst{7-4} = op7_4;
 }
 -def t2MLS: T2FourReg<
 -                (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
 -                "mls", "\t$Rd, $Rn, $Rm, $Ra",
 -                [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]>,
 -           Requires<[IsThumb2, UseMulOps]> {
 -  let Inst{31-27} = 0b11111;
 -  let Inst{26-23} = 0b0110;
 -  let Inst{22-20} = 0b000;
 -  let Inst{7-4} = 0b0001; // Multiply and Subtract
 -}
 +def t2MLA : T2FourRegMLA<0b0000, "mla",
 +                         [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm),
 +                                               rGPR:$Ra))]>;
 +def t2MLS: T2FourRegMLA<0b0001, "mls",
 +                        [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn,
 +                                                            rGPR:$Rm)))]>;
 // Extra precision multiplies with low / high results
 let hasSideEffects = 0 in {
 let isCommutable = 1 in {
 -def t2SMULL : T2MulLong<0b000, 0b0000,
 -                  (outs rGPR:$RdLo, rGPR:$RdHi),
 -                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
 -                   "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
 -
 -def t2UMULL : T2MulLong<0b010, 0b0000,
 -                  (outs rGPR:$RdLo, rGPR:$RdHi),
 -                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
 -                   "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
 +def t2SMULL : T2MulLong<0b000, 0b0000, "smull", []>;
 +def t2UMULL : T2MulLong<0b010, 0b0000, "umull", []>;
 } // isCommutable
 // Multiply + accumulate
 -def t2SMLAL : T2MlaLong<0b100, 0b0000,
 -                  (outs rGPR:$RdLo, rGPR:$RdHi),
 -                  (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
 -                  "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
 -                  RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
 -
 -def t2UMLAL : T2MlaLong<0b110, 0b0000,
 -                  (outs rGPR:$RdLo, rGPR:$RdHi),
 -                  (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
 -                  "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
 -                  RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
 -
 -def t2UMAAL : T2MulLong<0b110, 0b0110,
 -                  (outs rGPR:$RdLo, rGPR:$RdHi),
 -                  (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
 -                  "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
 -          RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
 -          Requires<[IsThumb2, HasDSP]>;
 +def t2SMLAL : T2MlaLong<0b100, 0b0000, "smlal">;
 +def t2UMLAL : T2MlaLong<0b110, 0b0000, "umlal">;
 +def t2UMAAL : T2MlaLong<0b110, 0b0110, "umaal">, Requires<[IsThumb2, HasDSP]>;
 } // hasSideEffects
 // Rounding variants of the below included for disassembly only
 // Most significant word multiply
 -def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
 -                  "smmul", "\t$Rd, $Rn, $Rm",
 -                  [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
 -          Requires<[IsThumb2, HasDSP]> {
 -  let Inst{31-27} = 0b11111;
 -  let Inst{26-23} = 0b0110;
 -  let Inst{22-20} = 0b101;
 -  let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
 -  let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
 -}
 -
 -def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
 -                  "smmulr", "\t$Rd, $Rn, $Rm", []>,
 -          Requires<[IsThumb2, HasDSP]> {
 +class T2SMMUL<bits<4> op7_4, string opc, list<dag> pattern>
 +  : T2ThreeReg<(outs rGPR:$Rd),
 +               (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
 +               opc, "\t$Rd, $Rn, $Rm", pattern>,
 +               Requires<[IsThumb2, HasDSP]> {
   let Inst{31-27} = 0b11111;
   let Inst{26-23} = 0b0110;
   let Inst{22-20} = 0b101;
   let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
 -  let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
 +  let Inst{7-4} = op7_4;
 }
 +def t2SMMUL : T2SMMUL<0b0000, "smmul", [(set rGPR:$Rd, (mulhs rGPR:$Rn,
 +                                                              rGPR:$Rm))]>;
 +def t2SMMULR : T2SMMUL<0b0001, "smmulr", []>;
 -def t2SMMLA : T2FourReg<
 -        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
 -                "smmla", "\t$Rd, $Rn, $Rm, $Ra",
 -                [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
 +class T2FourRegSMMLA<bits<3> op22_20, bits<4> op7_4, string opc,
 +                     list<dag> pattern>
 +  : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
 +              opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
               Requires<[IsThumb2, HasDSP, UseMulOps]> {
   let Inst{31-27} = 0b11111;
   let Inst{26-23} = 0b0110;
 -  let Inst{22-20} = 0b101;
 -  let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
 -}
 -
 -def t2SMMLAR: T2FourReg<
 -        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
 -                  "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
 -          Requires<[IsThumb2, HasDSP]> {
 -  let Inst{31-27} = 0b11111;
 -  let Inst{26-23} = 0b0110;
 -  let Inst{22-20} = 0b101;
 -  let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
 -}
 -
 -def t2SMMLS: T2FourReg<
 -        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
 -                "smmls", "\t$Rd, $Rn, $Rm, $Ra",
 -                [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
 -             Requires<[IsThumb2, HasDSP, UseMulOps]> {
 -  let Inst{31-27} = 0b11111;
 -  let Inst{26-23} = 0b0110;
 -  let Inst{22-20} = 0b110;
 -  let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
 -}
 -
 -def t2SMMLSR:T2FourReg<
 -        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
 -                "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
 -          Requires<[IsThumb2, HasDSP]> {
 -  let Inst{31-27} = 0b11111;
 -  let Inst{26-23} = 0b0110;
 -  let Inst{22-20} = 0b110;
 -  let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
 +  let Inst{22-20} = op22_20;
 +  let Inst{7-4} = op7_4;
 }
 -multiclass T2I_smul<string opc, SDNode opnode> {
 -  def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
 -              !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
 -              [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
 -                                      (sext_inreg rGPR:$Rm, i16)))]>,
 -          Requires<[IsThumb2, HasDSP]> {
 -    let Inst{31-27} = 0b11111;
 -    let Inst{26-23} = 0b0110;
 -    let Inst{22-20} = 0b001;
 -    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
 -    let Inst{7-6} = 0b00;
 -    let Inst{5-4} = 0b00;
 -  }
 -
 -  def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
 -              !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
 -              [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
 -                                      (sra rGPR:$Rm, (i32 16))))]>,
 -          Requires<[IsThumb2, HasDSP]> {
 -    let Inst{31-27} = 0b11111;
 -    let Inst{26-23} = 0b0110;
 -    let Inst{22-20} = 0b001;
 -    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
 -    let Inst{7-6} = 0b00;
 -    let Inst{5-4} = 0b01;
 -  }
 -
 -  def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
 -              !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
 -              [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
 -                                      (sext_inreg rGPR:$Rm, i16)))]>,
 -          Requires<[IsThumb2, HasDSP]> {
 -    let Inst{31-27} = 0b11111;
 -    let Inst{26-23} = 0b0110;
 -    let Inst{22-20} = 0b001;
 -    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
 -    let Inst{7-6} = 0b00;
 -    let Inst{5-4} = 0b10;
 -  }
 -
 -  def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
 -              !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
 -              [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
 -                                      (sra rGPR:$Rm, (i32 16))))]>,
 -          Requires<[IsThumb2, HasDSP]> {
 -    let Inst{31-27} = 0b11111;
 -    let Inst{26-23} = 0b0110;
 -    let Inst{22-20} = 0b001;
 -    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
 -    let Inst{7-6} = 0b00;
 -    let Inst{5-4} = 0b11;
 -  }
 -
 -  def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
 -              !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
 -              []>,
 -          Requires<[IsThumb2, HasDSP]> {
 -    let Inst{31-27} = 0b11111;
 -    let Inst{26-23} = 0b0110;
 -    let Inst{22-20} = 0b011;
 -    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
 -    let Inst{7-6} = 0b00;
 -    let Inst{5-4} = 0b00;
 -  }
 +def t2SMMLA : T2FourRegSMMLA<0b101, 0b0000, "smmla",
 +                [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>;
 +def t2SMMLAR: T2FourRegSMMLA<0b101, 0b0001, "smmlar", []>;
 +def t2SMMLS: T2FourRegSMMLA<0b110, 0b0000, "smmls",
 +                [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>;
 +def t2SMMLSR:T2FourRegSMMLA<0b110, 0b0001, "smmlsr", []>;
 -  def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
 -              !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
 -              []>,
 -          Requires<[IsThumb2, HasDSP]> {
 +class T2ThreeRegSMUL<bits<3> op22_20, bits<2> op5_4, string opc,
 +                     list<dag> pattern>
 +  : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, opc,
 +               "\t$Rd, $Rn, $Rm", pattern>,
 +    Requires<[IsThumb2, HasDSP]> {
     let Inst{31-27} = 0b11111;
     let Inst{26-23} = 0b0110;
 -    let Inst{22-20} = 0b011;
 +    let Inst{22-20} = op22_20;
     let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
     let Inst{7-6} = 0b00;
 -    let Inst{5-4} = 0b01;
 -  }
 -}
 -
 -
 -multiclass T2I_smla<string opc, SDNode opnode> {
 -  def BB : T2FourReg<
 -        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
 -              !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
 -              [(set rGPR:$Rd, (add rGPR:$Ra,
 -                               (opnode (sext_inreg rGPR:$Rn, i16),
 -                                       (sext_inreg rGPR:$Rm, i16))))]>,
 -           Requires<[IsThumb2, HasDSP, UseMulOps]> {
 +    let Inst{5-4} = op5_4;
 +}
 +
 +def t2SMULBB : T2ThreeRegSMUL<0b001, 0b00, "smulbb",
 +             [(set rGPR:$Rd, (mul (sext_inreg rGPR:$Rn, i16),
 +                                   (sext_inreg rGPR:$Rm, i16)))]>;
 +def t2SMULBT : T2ThreeRegSMUL<0b001, 0b01, "smulbt",
 +             [(set rGPR:$Rd, (mul (sext_inreg rGPR:$Rn, i16),
 +                                   (sra rGPR:$Rm, (i32 16))))]>;
 +def t2SMULTB : T2ThreeRegSMUL<0b001, 0b10, "smultb",
 +             [(set rGPR:$Rd, (mul (sra rGPR:$Rn, (i32 16)),
 +                                   (sext_inreg rGPR:$Rm, i16)))]>;
 +def t2SMULTT : T2ThreeRegSMUL<0b001, 0b11, "smultt",
 +             [(set rGPR:$Rd, (mul (sra rGPR:$Rn, (i32 16)),
 +                                   (sra rGPR:$Rm, (i32 16))))]>;
 +def t2SMULWB : T2ThreeRegSMUL<0b011, 0b00, "smulwb", []>;
 +def t2SMULWT : T2ThreeRegSMUL<0b011, 0b01, "smulwt", []>;
 +
 +class T2FourRegSMLA<bits<2> op5_4, string opc, list<dag> pattern>
 +  : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMUL16,
 +               opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
 +    Requires<[IsThumb2, HasDSP, UseMulOps]> {
     let Inst{31-27} = 0b11111;
     let Inst{26-23} = 0b0110;
     let Inst{22-20} = 0b001;
     let Inst{7-6} = 0b00;
 -    let Inst{5-4} = 0b00;
 -  }
 -
 -  def BT : T2FourReg<
 -       (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
 -             !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
 -             [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
 -                                                 (sra rGPR:$Rm, (i32 16)))))]>,
 -           Requires<[IsThumb2, HasDSP, UseMulOps]> {
 -    let Inst{31-27} = 0b11111;
 -    let Inst{26-23} = 0b0110;
 -    let Inst{22-20} = 0b001;
 -    let Inst{7-6} = 0b00;
 -    let Inst{5-4} = 0b01;
 -  }
 -
 -  def TB : T2FourReg<
 -        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
 -              !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
 -              [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
 -                                               (sext_inreg rGPR:$Rm, i16))))]>,
 -           Requires<[IsThumb2, HasDSP, UseMulOps]> {
 -    let Inst{31-27} = 0b11111;
 -    let Inst{26-23} = 0b0110;
 -    let Inst{22-20} = 0b001;
 -    let Inst{7-6} = 0b00;
 -    let Inst{5-4} = 0b10;
 -  }
 -
 -  def TT : T2FourReg<
 -        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
 -              !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
 -             [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
 -                                                 (sra rGPR:$Rm, (i32 16)))))]>,
 -           Requires<[IsThumb2, HasDSP, UseMulOps]> {
 -    let Inst{31-27} = 0b11111;
 -    let Inst{26-23} = 0b0110;
 -    let Inst{22-20} = 0b001;
 -    let Inst{7-6} = 0b00;
 -    let Inst{5-4} = 0b11;
 -  }
 -
 -  def WB : T2FourReg<
 -        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
 -              !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
 -              []>,
 -           Requires<[IsThumb2, HasDSP, UseMulOps]> {
 -    let Inst{31-27} = 0b11111;
 -    let Inst{26-23} = 0b0110;
 -    let Inst{22-20} = 0b011;
 -    let Inst{7-6} = 0b00;
 -    let Inst{5-4} = 0b00;
 -  }
 -
 -  def WT : T2FourReg<
 -        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
 -              !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
 -              []>,
 -           Requires<[IsThumb2, HasDSP, UseMulOps]> {
 -    let Inst{31-27} = 0b11111;
 -    let Inst{26-23} = 0b0110;
 -    let Inst{22-20} = 0b011;
 -    let Inst{7-6} = 0b00;
 -    let Inst{5-4} = 0b01;
 -  }
 -}
 -
 -defm t2SMUL : T2I_smul<"smul", mul>;
 -defm t2SMLA : T2I_smla<"smla", mul>;
 +    let Inst{5-4} = op5_4;
 +}
 +
 +def t2SMLABB : T2FourRegSMLA<0b00, "smlabb",
 +             [(set rGPR:$Rd, (add rGPR:$Ra,
 +                               (mul (sext_inreg rGPR:$Rn, i16),
 +                                     (sext_inreg rGPR:$Rm, i16))))]>;
 +def t2SMLABT : T2FourRegSMLA<0b01, "smlabt",
 +             [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sext_inreg rGPR:$Rn, i16),
 +                                                 (sra rGPR:$Rm, (i32 16)))))]>;
 +def t2SMLATB : T2FourRegSMLA<0b10, "smlatb",
 +             [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)),
 +                                                (sext_inreg rGPR:$Rm, i16))))]>;
 +def t2SMLATT : T2FourRegSMLA<0b11, "smlatt",
 +             [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)),
 +                                                 (sra rGPR:$Rm, (i32 16)))))]>;
 +def t2SMLAWB : T2FourRegSMLA<0b00, "smlawb", []> {
 +  let Inst{22-20} = 0b011;
 +}
 +def t2SMLAWT : T2FourRegSMLA<0b01, "smlawt", []> {
 +  let Inst{22-20} = 0b011;
 +}
 +
 +class T2SMLAL<bits<3> op22_20, bits<4> op7_4, string opc, list<dag> pattern>
 +  : T2FourReg_mac<1, op22_20, op7_4,
 +                  (outs rGPR:$Ra, rGPR:$Rd),
 +                  (ins rGPR:$Rn, rGPR:$Rm),
 +                  IIC_iMAC64, opc, "\t$Ra, $Rd, $Rn, $Rm", []>,
 +                  Requires<[IsThumb2, HasDSP]>;
 // Halfword multiple accumulate long: SMLAL<x><y>
 -def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
 -         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
 -           [/* For disassembly only; pattern left blank */]>,
 -          Requires<[IsThumb2, HasDSP]>;
 -def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
 -         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
 -           [/* For disassembly only; pattern left blank */]>,
 -          Requires<[IsThumb2, HasDSP]>;
 -def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
 -         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
 -           [/* For disassembly only; pattern left blank */]>,
 -          Requires<[IsThumb2, HasDSP]>;
 -def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
 -         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
 -           [/* For disassembly only; pattern left blank */]>,
 -          Requires<[IsThumb2, HasDSP]>;
 -
 -// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
 -def t2SMUAD: T2ThreeReg_mac<
 -            0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
 -            IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
 -          Requires<[IsThumb2, HasDSP]> {
 +def t2SMLALBB : T2SMLAL<0b100, 0b1000, "smlalbb", []>;
 +def t2SMLALBT : T2SMLAL<0b100, 0b1001, "smlalbt", []>;
 +def t2SMLALTB : T2SMLAL<0b100, 0b1010, "smlaltb", []>;
 +def t2SMLALTT : T2SMLAL<0b100, 0b1011, "smlaltt", []>;
 +
 +class T2DualHalfMul<bits<3> op22_20, bits<4> op7_4, string opc>
 +  : T2ThreeReg_mac<0, op22_20, op7_4,
 +                   (outs rGPR:$Rd),
 +                   (ins rGPR:$Rn, rGPR:$Rm),
 +                   IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm", []>,
 +                   Requires<[IsThumb2, HasDSP]> {
   let Inst{15-12} = 0b1111;
 }
 -def t2SMUADX:T2ThreeReg_mac<
 -            0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
 -            IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
 -          Requires<[IsThumb2, HasDSP]> {
 -  let Inst{15-12} = 0b1111;
 -}
 -def t2SMUSD: T2ThreeReg_mac<
 -            0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
 -            IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
 -          Requires<[IsThumb2, HasDSP]> {
 -  let Inst{15-12} = 0b1111;
 -}
 -def t2SMUSDX:T2ThreeReg_mac<
 -            0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
 -            IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
 -          Requires<[IsThumb2, HasDSP]> {
 -  let Inst{15-12} = 0b1111;
 -}
 -def t2SMLAD   : T2FourReg_mac<
 -            0, 0b010, 0b0000, (outs rGPR:$Rd),
 -            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
 -            "\t$Rd, $Rn, $Rm, $Ra", []>,
 -          Requires<[IsThumb2, HasDSP]>;
 -def t2SMLADX  : T2FourReg_mac<
 -            0, 0b010, 0b0001, (outs rGPR:$Rd),
 -            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
 -            "\t$Rd, $Rn, $Rm, $Ra", []>,
 -          Requires<[IsThumb2, HasDSP]>;
 -def t2SMLSD   : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
 -            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
 -            "\t$Rd, $Rn, $Rm, $Ra", []>,
 -          Requires<[IsThumb2, HasDSP]>;
 -def t2SMLSDX  : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
 -            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
 -            "\t$Rd, $Rn, $Rm, $Ra", []>,
 -          Requires<[IsThumb2, HasDSP]>;
 -def t2SMLALD  : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
 -                        (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
 -                        "\t$Ra, $Rd, $Rn, $Rm", []>,
 -          Requires<[IsThumb2, HasDSP]>;
 -def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
 -                        (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
 -                        "\t$Ra, $Rd, $Rn, $Rm", []>,
 -          Requires<[IsThumb2, HasDSP]>;
 -def t2SMLSLD  : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
 -                        (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
 -                        "\t$Ra, $Rd, $Rn, $Rm", []>,
 -          Requires<[IsThumb2, HasDSP]>;
 -def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
 -                        (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
 -                        "\t$Ra, $Rd, $Rn, $Rm", []>,
 -          Requires<[IsThumb2, HasDSP]>;
 +
 +// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
 +def t2SMUAD: T2DualHalfMul<0b010, 0b0000, "smuad">;
 +def t2SMUADX: T2DualHalfMul<0b010, 0b0001, "smuadx">;
 +def t2SMUSD: T2DualHalfMul<0b100, 0b0000, "smusd">;
 +def t2SMUSDX: T2DualHalfMul<0b100, 0b0001, "smusdx">;
 +
 +class T2DualHalfMulAdd<bits<3> op22_20, bits<4> op7_4, string opc>
 +  : T2FourReg_mac<0, op22_20, op7_4,
 +                  (outs rGPR:$Rd),
 +                  (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra),
 +                  IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm, $Ra", []>,
 +                  Requires<[IsThumb2, HasDSP]>;
 +
 +def t2SMLAD   : T2DualHalfMulAdd<0b010, 0b0000, "smlad">;
 +def t2SMLADX  : T2DualHalfMulAdd<0b010, 0b0001, "smladx">;
 +def t2SMLSD   : T2DualHalfMulAdd<0b100, 0b0000, "smlsd">;
 +def t2SMLSDX  : T2DualHalfMulAdd<0b100, 0b0001, "smlsdx">;
 +
 +class T2DualHalfMulAddLong<bits<3> op22_20, bits<4> op7_4, string opc>
 +  : T2FourReg_mac<1, op22_20, op7_4,
 +                  (outs rGPR:$Ra, rGPR:$Rd),
 +                  (ins rGPR:$Rn, rGPR:$Rm),
 +                  IIC_iMAC64, opc, "\t$Ra, $Rd, $Rn, $Rm", []>,
 +                  Requires<[IsThumb2, HasDSP]>;
 +
 +def t2SMLALD  : T2DualHalfMulAddLong<0b100, 0b1100, "smlald">;
 +def t2SMLALDX : T2DualHalfMulAddLong<0b100, 0b1101, "smlaldx">;
 +def t2SMLSLD  : T2DualHalfMulAddLong<0b101, 0b1100, "smlsld">;
 +def t2SMLSLDX : T2DualHalfMulAddLong<0b101, 0b1101, "smlsldx">;
 //===----------------------------------------------------------------------===//
 //  Division Instructions.
 diff --git a/test/CodeGen/ARM/longMAC.ll b/test/CodeGen/ARM/longMAC.ll
 index cc2d745..8edf965 100644
 --- a/test/CodeGen/ARM/longMAC.ll
 +++ b/test/CodeGen/ARM/longMAC.ll
@@ -2,6 +2,8 @@
 ; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s --check-prefix=CHECK-V7-LE
 ; RUN: llc -mtriple=armeb-eabi %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
 ; RUN: llc -mtriple=armebv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V7-BE
 +; RUN: llc -mtriple=thumbv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V7-THUMB
 +; RUN: llc -mtriple=thumbebv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V7-THUMB-BE
 ; Check generated signed and unsigned multiply accumulate long.
 define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {
@@ -118,8 +120,18 @@ define i64 @MACLongTest8(i64 %acc, i32 %lhs, i32 %rhs) {
 define i64 @MACLongTest9(i32 %lhs, i32 %rhs, i32 %lo, i32 %hi) {
 ;CHECK-LABEL: MACLongTest9:
 -;CHECK-V7-LE:umaal
 -;CHECK-V7-BE:umaal
 +;CHECK-V7-LE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
 +;CHECK-V7-LE: mov r0, [[RDLO]]
 +;CHECK-V7-LE: mov r1, [[RDHI]]
 +;CHECK-V7-BE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
 +;CHECK-V7-BE: mov r0, [[RDHI]]
 +;CHECK-V7-BE: mov r1, [[RDLO]]
 +;CHECK-V7-THUMB: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
 +;CHECK-V7-THUMB: mov r0, [[RDLO]]
 +;CHECK-V7-THUMB: mov r1, [[RDHI]]
 +;CHECK-V7-THUMB-BE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
 +;CHECK-V7-THUMB-BE: mov r0, [[RDHI]]
 +;CHECK-V7-THUMB-BE: mov r1, [[RDLO]]
 ;CHECK-NOT:umaal
   %conv = zext i32 %lhs to i64
   %conv1 = zext i32 %rhs to i64
@@ -133,8 +145,18 @@ define i64 @MACLongTest9(i32 %lhs, i32 %rhs, i32 %lo, i32 %hi) {
 define i64 @MACLongTest10(i32 %lhs, i32 %rhs, i32 %lo, i32 %hi) {
 ;CHECK-LABEL: MACLongTest10:
 -;CHECK-V7-LE:umaal
 -;CHECK-V7-BE:umaal
 +;CHECK-V7-LE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
 +;CHECK-V7-LE: mov r0, [[RDLO]]
 +;CHECK-V7-LE: mov r1, [[RDHI]]
 +;CHECK-V7-BE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
 +;CHECK-V7-BE: mov r0, [[RDHI]]
 +;CHECK-V7-BE: mov r1, [[RDLO]]
 +;CHECK-V7-THUMB: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
 +;CHECK-V7-THUMB: mov r0, [[RDLO]]
 +;CHECK-V7-THUMB: mov r1, [[RDHI]]
 +;CHECK-V7-THUMB-BE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
 +;CHECK-V7-THUMB-BE: mov r0, [[RDHI]]
 +;CHECK-V7-THUMB-BE: mov r1, [[RDLO]]
 ;CHECK-NOT:umaal
   %conv = zext i32 %lhs to i64
   %conv1 = zext i32 %rhs to i64
 -- 
 2.7.4
@@ -1,133 +0,0 @@
 From 9ce71bff387ce9e30adddf72a29874bbb058dd5a Mon Sep 17 00:00:00 2001
 From: Sam Parker <sam.parker@arm.com>
 Date: Mon, 25 Jul 2016 09:20:20 +0000
 Subject: [PATCH 2/3] [ARM] Enable ISel of SMMLS for ARM and Thumb2
 Use ISelDAGToDAG to recognise the SMMLS instruction pattern.
 Differential Revision: https://reviews.llvm.org/D22562
 Cherry-picked from SVN trunk commit 276624, git mirror commit
 161eae5670.
 ---
 lib/Target/ARM/ARMISelDAGToDAG.cpp | 30 ++++++++++++++++++++++++++++++
 lib/Target/ARM/ARMInstrThumb2.td   |  9 ++++-----
 test/CodeGen/ARM/smml.ll           | 36 ++++++++++++++++++++++++++++++++++--
 3 files changed, 68 insertions(+), 7 deletions(-)
 diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
 index 20db3d3..96cb691 100644
 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
 +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -3037,6 +3037,36 @@ void ARMDAGToDAGISel::Select(SDNode *N) {
       return;
     }
   }
 +  case ARMISD::SUBE: {
 +    if (!Subtarget->hasV6Ops())
 +      break;
 +    // Look for a pattern to match SMMLS
 +    // (sube a, (smul_loHi a, b), (subc 0, (smul_LOhi(a, b))))
 +    if (N->getOperand(1).getOpcode() != ISD::SMUL_LOHI ||
 +        N->getOperand(2).getOpcode() != ARMISD::SUBC)
 +      break;
 +
 +    if (Subtarget->isThumb())
 +      assert(Subtarget->hasThumb2() &&
 +             "This pattern should not be generated for Thumb");
 +
 +    SDValue SmulLoHi = N->getOperand(1);
 +    SDValue Subc = N->getOperand(2);
 +    auto *Zero = dyn_cast<ConstantSDNode>(Subc.getOperand(0));
 +
 +    if (!Zero || Zero->getZExtValue() != 0 ||
 +        Subc.getOperand(1) != SmulLoHi.getValue(0) ||
 +        N->getOperand(1) != SmulLoHi.getValue(1) ||
 +        N->getOperand(2) != Subc.getValue(1))
 +      break;
 +
 +    unsigned Opc = Subtarget->isThumb2() ? ARM::t2SMMLS : ARM::SMMLS;
 +    SDValue Ops[] = { SmulLoHi.getOperand(0), SmulLoHi.getOperand(1),
 +                      N->getOperand(0), getAL(CurDAG, dl),
 +                      CurDAG->getRegister(0, MVT::i32) };
 +    ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops));
 +    return;
 +  }
   case ISD::LOAD: {
     if (Subtarget->isThumb() && Subtarget->hasThumb2()) {
       if (tryT2IndexedLoad(N))
 diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
 index 64f5dad..599b552 100644
 --- a/lib/Target/ARM/ARMInstrThumb2.td
 +++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -2606,12 +2606,11 @@ class T2FourRegSMMLA<bits<3> op22_20, bits<4> op7_4, string opc,
   let Inst{7-4} = op7_4;
 }
 -def t2SMMLA : T2FourRegSMMLA<0b101, 0b0000, "smmla",
 +def t2SMMLA :   T2FourRegSMMLA<0b101, 0b0000, "smmla",
                 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>;
 -def t2SMMLAR: T2FourRegSMMLA<0b101, 0b0001, "smmlar", []>;
 -def t2SMMLS: T2FourRegSMMLA<0b110, 0b0000, "smmls",
 -                [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>;
 -def t2SMMLSR:T2FourRegSMMLA<0b110, 0b0001, "smmlsr", []>;
 +def t2SMMLAR:   T2FourRegSMMLA<0b101, 0b0001, "smmlar", []>;
 +def t2SMMLS:    T2FourRegSMMLA<0b110, 0b0000, "smmls", []>;
 +def t2SMMLSR:   T2FourRegSMMLA<0b110, 0b0001, "smmlsr", []>;
 class T2ThreeRegSMUL<bits<3> op22_20, bits<2> op5_4, string opc,
                      list<dag> pattern>
 diff --git a/test/CodeGen/ARM/smml.ll b/test/CodeGen/ARM/smml.ll
 index fc73eb7..807445f 100644
 --- a/test/CodeGen/ARM/smml.ll
 +++ b/test/CodeGen/ARM/smml.ll
@@ -1,8 +1,20 @@
 -; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
 +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=CHECK
 +; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V6
 +; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V7
 +; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s -check-prefix=CHECK-THUMB
 +; RUN: llc -mtriple=thumbv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK-THUMB
 +; RUN: llc -mtriple=thumbv6t2-eabi %s -o - | FileCheck %s -check-prefix=CHECK-THUMBV6T2
 +; RUN: llc -mtriple=thumbv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK-THUMBV7
 -define i32 @f(i32 %a, i32 %b, i32 %c) nounwind readnone ssp {
 +define i32 @Test0(i32 %a, i32 %b, i32 %c) nounwind readnone ssp {
 entry:
 +; CHECK-LABEL: Test0
 ; CHECK-NOT: smmls
 +; CHECK-V6-NOT: smmls
 +; CHECK-V7-NOT: smmls
 +; CHECK_THUMB-NOT: smmls
 +; CHECK-THUMBV6T2-NOT: smmls
 +; CHECK-THUMBV7-NOT: smmls
   %conv4 = zext i32 %a to i64
   %conv1 = sext i32 %b to i64
   %conv2 = sext i32 %c to i64
@@ -12,3 +24,23 @@ entry:
   %conv3 = trunc i64 %sub to i32
   ret i32 %conv3
 }
 +
 +define i32 @Test1(i32 %a, i32 %b, i32 %c) {
 +;CHECK-LABEL: Test1
 +;CHECK-NOT: smmls
 +;CHECK-THUMB-NOT: smmls
 +;CHECK-V6: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
 +;CHECK-V7: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
 +;CHECK-THUMBV6T2: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
 +;CHECK-THUMBV7: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
 +entry:
 +  %conv = sext i32 %b to i64
 +  %conv1 = sext i32 %c to i64
 +  %mul = mul nsw i64 %conv1, %conv
 +  %conv26 = zext i32 %a to i64
 +  %shl = shl nuw i64 %conv26, 32
 +  %sub = sub nsw i64 %shl, %mul
 +  %shr7 = lshr i64 %sub, 32
 +  %conv3 = trunc i64 %shr7 to i32
 +  ret i32 %conv3
 +}
 -- 
 2.7.4
@@ -1,70 +0,0 @@
 From 3b940b64588ea7df1c473021abe3ee3bf32a8294 Mon Sep 17 00:00:00 2001
 From: Renato Golin <renato.golin@linaro.org>
 Date: Wed, 27 Jul 2016 12:31:58 +0000
 Subject: [PATCH 3/3] [ARM] Set a non-conflicting comment character for
 assembly in MSVC mode
 MIME-Version: 1.0
 Content-Type: text/plain; charset=UTF-8
 Content-Transfer-Encoding: 8bit
 Currently, for ARMCOFFMCAsmInfoMicrosoft, no comment character is set, thus the
 idefault, '#', is used.
 The hash character doesn't work as comment character in ARM assembly, since '#'
 is used for immediate values.
 The comment character is set to ';', which is the comment character used by MS
 armasm.exe. (The microsoft armasm.exe uses a different directive syntax than
 what LLVM currently supports though, similar to ARM's armasm.)
 This allows inline assembly with immediate constants to be built (and brings the
 assembly output from clang -S closer to being possible to assemble).
 A test is added that verifies that ';' is correctly interpreted as comments in
 this mode, and verifies that assembling code that includes literal constants
 with a '#' works.
 Patch by Martin Storsjö.
 Cherry-picked from SVN trunk commit 276859, git mirror commit
 b9c61f0c0404.
 ---
 lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp |  1 +
 test/MC/ARM/Windows/literals-comments.s      | 13 +++++++++++++
 2 files changed, 14 insertions(+)
 create mode 100644 test/MC/ARM/Windows/literals-comments.s
 diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
 index 53cd29a..1e062ad 100644
 --- a/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
 +++ b/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
@@ -90,6 +90,7 @@ ARMCOFFMCAsmInfoMicrosoft::ARMCOFFMCAsmInfoMicrosoft() {
   PrivateGlobalPrefix = "$M";
   PrivateLabelPrefix = "$M";
 +  CommentString = ";";
 }
 void ARMCOFFMCAsmInfoGNU::anchor() { }
 diff --git a/test/MC/ARM/Windows/literals-comments.s b/test/MC/ARM/Windows/literals-comments.s
 new file mode 100644
 index 0000000..be98874
 --- /dev/null
 +++ b/test/MC/ARM/Windows/literals-comments.s
@@ -0,0 +1,13 @@
 +; RUN: llvm-mc -triple armv7-windows-msvc -filetype obj -o - %s
 +
 +  .syntax unified
 +  .thumb
 +
 +  .text
 +
 +  .global function
 +  .thumb_func
 +function:
 +  ; this is a comment
 +  mov r0, #42 ; this # was not
 +  bx lr
 -- 
 2.7.4
@@ -1,7 +1,7 @@
-From e809b3e41dd5d4ba55c1b941f2b4f72b408b4c2e Mon Sep 17 00:00:00 2001
+From 23fe55b344184414deed5713cc3033e1706056aa Mon Sep 17 00:00:00 2001
 From: Martell Malone <martellmalone@gmail.com>
 Date: Tue, 9 Aug 2016 17:52:46 -0700
-Subject: [PATCH 4/6] genlib: named as llvm-dlltool
+Subject: [PATCH 1/3] genlib: named as llvm-dlltool
 A PE COFF spec compliant import library generator.
 Intended to be used with mingw-w64.
@@ -63,15 +63,16 @@ index 0000000..79fb7b7
 +
 +#endif
 diff --git a/lib/CMakeLists.txt b/lib/CMakeLists.txt
-index 9449421..03988a6 100644
+index 7654954..bebb628 100644
 --- a/lib/CMakeLists.txt
 +++ b/lib/CMakeLists.txt
-@@ -20,4 +20,5 @@ add_subdirectory(LineEditor)
+@@ -21,5 +21,6 @@ add_subdirectory(LineEditor)
 add_subdirectory(ProfileData)
 add_subdirectory(Fuzzer)
 add_subdirectory(Passes)
 +add_subdirectory(DLLDriver)
 add_subdirectory(LibDriver)
 add_subdirectory(XRay)
 diff --git a/lib/DLLDriver/CMakeLists.txt b/lib/DLLDriver/CMakeLists.txt
 new file mode 100644
 index 0000000..91fb2f0
@@ -1382,10 +1383,10 @@ index 0000000..62f33f3
 +def out: JoinedOrSeparate<["-"], "o">, HelpText<"Set output file">;
 +def dll: JoinedOrSeparate<["-"], "d">, HelpText<"Set dll name">;
 diff --git a/lib/Object/ArchiveWriter.cpp b/lib/Object/ArchiveWriter.cpp
-index 5357326..46b9d97 100644
+index f8e3c5a..d5f067e 100644
 --- a/lib/Object/ArchiveWriter.cpp
 +++ b/lib/Object/ArchiveWriter.cpp
-@@ -273,7 +273,8 @@ writeSymbolTable(raw_fd_ostream &Out, object::Archive::Kind Kind,
+@@ -299,7 +299,8 @@ writeSymbolTable(raw_fd_ostream &Out, object::Archive::Kind Kind,
         continue;
       if (!(Symflags & object::SymbolRef::SF_Global))
         continue;
@@ -1396,7 +1397,7 @@ index 5357326..46b9d97 100644
       unsigned NameOffset = NameOS.tell();
 diff --git a/tools/llvm-ar/CMakeLists.txt b/tools/llvm-ar/CMakeLists.txt
-index 86233df..94cc205 100644
+index 3bb0c8f..14732b4 100644
 --- a/tools/llvm-ar/CMakeLists.txt
 +++ b/tools/llvm-ar/CMakeLists.txt
@@ -1,6 +1,7 @@
@@ -1407,13 +1408,13 @@ index 86233df..94cc205 100644
   LibDriver
   Object
   Support
-@@ -12,3 +13,4 @@ add_llvm_tool(llvm-ar
+@@ -15,3 +16,4 @@ add_llvm_tool(llvm-ar
 add_llvm_tool_symlink(llvm-ranlib llvm-ar)
 add_llvm_tool_symlink(llvm-lib llvm-ar)
 +add_llvm_tool_symlink(llvm-dlltool llvm-ar)
 diff --git a/tools/llvm-ar/llvm-ar.cpp b/tools/llvm-ar/llvm-ar.cpp
-index 865152b..936c417 100644
+index b99a396..23e323c 100644
 --- a/tools/llvm-ar/llvm-ar.cpp
 +++ b/tools/llvm-ar/llvm-ar.cpp
@@ -16,6 +16,7 @@
@@ -1424,7 +1425,7 @@ index 865152b..936c417 100644
 #include "llvm/LibDriver/LibDriver.h"
 #include "llvm/Object/Archive.h"
 #include "llvm/Object/ArchiveWriter.h"
-@@ -827,6 +828,9 @@ int main(int argc, char **argv) {
+@@ -850,6 +851,9 @@ int main(int argc, char **argv) {
   llvm::InitializeAllAsmParsers();
   StringRef Stem = sys::path::stem(ToolName);
@@ -1434,7 +1435,7 @@ index 865152b..936c417 100644
   if (Stem.find("ranlib") == StringRef::npos &&
       Stem.find("lib") != StringRef::npos)
     return libDriverMain(makeArrayRef(argv, argc));
-@@ -842,5 +846,5 @@ int main(int argc, char **argv) {
+@@ -865,5 +869,5 @@ int main(int argc, char **argv) {
     return ranlib_main();
   if (Stem.find("ar") != StringRef::npos)
     return ar_main();
@@ -1,7 +1,7 @@
-From 3de4f391131ab56e03622bf3bbb152c29bdc293e Mon Sep 17 00:00:00 2001
+From 44892d7c172014a45e9a191fc36b2d4cca343890 Mon Sep 17 00:00:00 2001
 From: Martell Malone <martellmalone@gmail.com>
 Date: Tue, 16 Aug 2016 13:05:23 -0700
-Subject: [PATCH 5/6] COFF: Fix short import lib import name type bitshift
+Subject: [PATCH 2/3] COFF: Fix short import lib import name type bitshift
 llvm-readobj: Support short import objects from within an archive
 The import magic was previous just checked against the archive as a whole
@@ -11,31 +11,13 @@ Offset: 18 Size 2 bits Name: Type
 Offset: 20 Size 3 bits Name: Name Type
 Offset: 20 added based on 18+2
 Cherry-picked from SVN trunk commit 283055, git mirror commit
 d17dee59d1351.
 ---
 include/llvm/Support/COFF.h                            |   2 +-
 .../llvm-readobj/Inputs/imports.mangle.coff-x86_64     | Bin 0 -> 2108 bytes
 test/tools/llvm-readobj/imports-mangle.test            |  17 +++++++++++++++++
- tools/llvm-readobj/llvm-readobj.cpp                    |   2 ++
+ 2 files changed, 17 insertions(+)
 4 files changed, 20 insertions(+), 1 deletion(-)
 create mode 100644 test/tools/llvm-readobj/Inputs/imports.mangle.coff-x86_64
 create mode 100644 test/tools/llvm-readobj/imports-mangle.test
 diff --git a/include/llvm/Support/COFF.h b/include/llvm/Support/COFF.h
 index 7dad3e8..1ca781b9 100644
 --- a/include/llvm/Support/COFF.h
 +++ b/include/llvm/Support/COFF.h
@@ -657,7 +657,7 @@ namespace COFF {
     }
     ImportNameType getNameType() const {
 -      return static_cast<ImportNameType>((TypeInfo & 0x1C) >> 3);
 +      return static_cast<ImportNameType>((TypeInfo & 0x1C) >> 2);
     }
   };
 diff --git a/test/tools/llvm-readobj/Inputs/imports.mangle.coff-x86_64 b/test/tools/llvm-readobj/Inputs/imports.mangle.coff-x86_64
 new file mode 100644
 index 0000000000000000000000000000000000000000..af6e583a31b953d1c9451266b09bee50093b8d54
@@ -81,19 +63,6 @@ index 0000000..211fc57
 +X64:      Name type: ordinal
 +X64-NEXT:   Symbol: __imp_sym2
 +X64-NEXT:   Symbol: sym2
 diff --git a/tools/llvm-readobj/llvm-readobj.cpp b/tools/llvm-readobj/llvm-readobj.cpp
 index c293919..bb5ad37 100644
 --- a/tools/llvm-readobj/llvm-readobj.cpp
 +++ b/tools/llvm-readobj/llvm-readobj.cpp
@@ -450,6 +450,8 @@ static void dumpArchive(const Archive *Arc) {
     }
     if (ObjectFile *Obj = dyn_cast<ObjectFile>(&*ChildOrErr.get()))
       dumpObject(Obj);
 +    else if (COFFImportFile *Import = dyn_cast<COFFImportFile>(&*ChildOrErr.get()))
 +      dumpCOFFImportFile(Import);
     else
       reportError(Arc->getFileName(), readobj_error::unrecognized_file_format);
   }
 -- 
 2.7.4
@@ -1,7 +1,7 @@
-From 2743b4757dcb3ef66dc9e7b64034b0f8b94ff66a Mon Sep 17 00:00:00 2001
+From b0e293af0bdcb46da3ec6fd90d67e1deaa7ab907 Mon Sep 17 00:00:00 2001
 From: Martell Malone <martellmalone@gmail.com>
 Date: Tue, 16 Aug 2016 12:55:01 -0700
-Subject: [PATCH 6/6] mingw-w64: use MSVC style ByteAlignment
+Subject: [PATCH 3/3] mingw-w64: use MSVC style ByteAlignment
 We can do alignment without -aligncomm derectives in PE COFF
 Until we support GNU style in lld we should use this
@@ -10,10 +10,10 @@ Until we support GNU style in lld we should use this
 1 file changed, 2 insertions(+), 2 deletions(-)
 diff --git a/lib/MC/WinCOFFStreamer.cpp b/lib/MC/WinCOFFStreamer.cpp
-index 5c6407e..f86cbc5 100644
+index 6383d87..06a5aef 100644
 --- a/lib/MC/WinCOFFStreamer.cpp
 +++ b/lib/MC/WinCOFFStreamer.cpp
-@@ -208,7 +208,7 @@ void MCWinCOFFStreamer::EmitCommonSymbol(MCSymbol *S, uint64_t Size,
+@@ -217,7 +217,7 @@ void MCWinCOFFStreamer::EmitCommonSymbol(MCSymbol *S, uint64_t Size,
   auto *Symbol = cast<MCSymbolCOFF>(S);
   const Triple &T = getContext().getObjectFileInfo()->getTargetTriple();
@@ -22,7 +22,7 @@ index 5c6407e..f86cbc5 100644
     if (ByteAlignment > 32)
       report_fatal_error("alignment is limited to 32-bytes");
-@@ -220,7 +220,7 @@ void MCWinCOFFStreamer::EmitCommonSymbol(MCSymbol *S, uint64_t Size,
+@@ -229,7 +229,7 @@ void MCWinCOFFStreamer::EmitCommonSymbol(MCSymbol *S, uint64_t Size,
   Symbol->setExternal(true);
   Symbol->setCommon(Size, ByteAlignment);
@@ -1,361 +0,0 @@
 From ed632cebfe6b046152e3f353c7a70ae4c4efea52 Mon Sep 17 00:00:00 2001
 From: Martin Storsjo <martin@martin.st>
 Date: Fri, 7 Oct 2016 13:28:53 +0000
 Subject: [PATCH 7/9] [ARM] Reapply: Use __rt_div functions for divrem on
 Windows
 Reapplying r283383 after revert in r283442. The additional fix
 is a getting rid of a stray space in a function name, in the
 refactoring part of the commit.
 This avoids falling back to calling out to the GCC rem functions
 (__moddi3, __umoddi3) when targeting Windows.
 The __rt_div functions have flipped the two arguments compared
 to the __aeabi_divmod functions. To match MSVC, we emit a
 check for division by zero before actually calling the library
 function (even if the library function itself also might do
 the same check).
 Not all calls to __rt_div functions for division are currently
 merged with calls to the same function with the same parameters
 for the remainder. This is more wasteful than a div + mls as before,
 but avoids calls to __moddi3.
 Differential Revision: https://reviews.llvm.org/D25332
 Cherry-picked from SVN trunk commit 283550, git mirror commit
 c3339a54ac77.
 ---
 lib/Target/ARM/ARMISelLowering.cpp | 66 ++++++++++++++++++++++++++------------
 test/CodeGen/ARM/Windows/dbzchk.ll |  2 +-
 test/CodeGen/ARM/divmod-eabi.ll    | 56 +++++++++++++-------------------
 3 files changed, 68 insertions(+), 56 deletions(-)
 diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
 index 3cfcb1e..8db9f54 100644
 --- a/lib/Target/ARM/ARMISelLowering.cpp
 +++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -803,19 +803,26 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::UREM,  MVT::i32, Expand);
   // Register based DivRem for AEABI (RTABI 4.2)
   if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
 -      Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI()) {
 +      Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
 +      Subtarget->isTargetWindows()) {
     setOperationAction(ISD::SREM, MVT::i64, Custom);
     setOperationAction(ISD::UREM, MVT::i64, Custom);
     HasStandaloneRem = false;
 -    setLibcallName(RTLIB::SDIVREM_I8,  "__aeabi_idivmod");
 -    setLibcallName(RTLIB::SDIVREM_I16, "__aeabi_idivmod");
 -    setLibcallName(RTLIB::SDIVREM_I32, "__aeabi_idivmod");
 -    setLibcallName(RTLIB::SDIVREM_I64, "__aeabi_ldivmod");
 -    setLibcallName(RTLIB::UDIVREM_I8,  "__aeabi_uidivmod");
 -    setLibcallName(RTLIB::UDIVREM_I16, "__aeabi_uidivmod");
 -    setLibcallName(RTLIB::UDIVREM_I32, "__aeabi_uidivmod");
 -    setLibcallName(RTLIB::UDIVREM_I64, "__aeabi_uldivmod");
 +    for (const auto &LC :
 +         {RTLIB::SDIVREM_I8, RTLIB::SDIVREM_I16, RTLIB::SDIVREM_I32})
 +      setLibcallName(LC, Subtarget->isTargetWindows() ? "__rt_sdiv"
 +                                                      : "__aeabi_idivmod");
 +    setLibcallName(RTLIB::SDIVREM_I64, Subtarget->isTargetWindows()
 +                                           ? "__rt_sdiv64"
 +                                           : "__aeabi_ldivmod");
 +    for (const auto &LC :
 +         {RTLIB::UDIVREM_I8, RTLIB::UDIVREM_I16, RTLIB::UDIVREM_I32})
 +      setLibcallName(LC, Subtarget->isTargetWindows() ? "__rt_udiv"
 +                                                      : "__aeabi_uidivmod");
 +    setLibcallName(RTLIB::UDIVREM_I64, Subtarget->isTargetWindows()
 +                                           ? "__rt_udiv64"
 +                                           : "__aeabi_uldivmod");
     setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::ARM_AAPCS);
     setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::ARM_AAPCS);
@@ -7029,6 +7036,19 @@ SDValue ARMTargetLowering::LowerDIV_Windows(SDValue Op, SelectionDAG &DAG,
   return LowerWindowsDIVLibCall(Op, DAG, Signed, DBZCHK);
 }
 +static SDValue WinDBZCheckDenominator(SelectionDAG &DAG, SDNode *N, SDValue InChain) {
 +  SDLoc DL(N);
 +  SDValue Op = N->getOperand(1);
 +  if (N->getValueType(0) == MVT::i32)
 +    return DAG.getNode(ARMISD::WIN__DBZCHK, DL, MVT::Other, InChain, Op);
 +  SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Op,
 +                           DAG.getConstant(0, DL, MVT::i32));
 +  SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Op,
 +                           DAG.getConstant(1, DL, MVT::i32));
 +  return DAG.getNode(ARMISD::WIN__DBZCHK, DL, MVT::Other, InChain,
 +                     DAG.getNode(ISD::OR, DL, MVT::i32, Lo, Hi));
 +}
 +
 void ARMTargetLowering::ExpandDIV_Windows(
     SDValue Op, SelectionDAG &DAG, bool Signed,
     SmallVectorImpl<SDValue> &Results) const {
@@ -7039,14 +7059,7 @@ void ARMTargetLowering::ExpandDIV_Windows(
          "unexpected type for custom lowering DIV");
   SDLoc dl(Op);
 -  SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op.getOperand(1),
 -                           DAG.getConstant(0, dl, MVT::i32));
 -  SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op.getOperand(1),
 -                           DAG.getConstant(1, dl, MVT::i32));
 -  SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, Lo, Hi);
 -
 -  SDValue DBZCHK =
 -      DAG.getNode(ARMISD::WIN__DBZCHK, dl, MVT::Other, DAG.getEntryNode(), Or);
 +  SDValue DBZCHK = WinDBZCheckDenominator(DAG, Op.getNode(), DAG.getEntryNode());
   SDValue Result = LowerWindowsDIVLibCall(Op, DAG, Signed, DBZCHK);
@@ -12043,7 +12056,7 @@ static RTLIB::Libcall getDivRemLibcall(
 }
 static TargetLowering::ArgListTy getDivRemArgList(
 -    const SDNode *N, LLVMContext *Context) {
 +    const SDNode *N, LLVMContext *Context, const ARMSubtarget *Subtarget) {
   assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||
           N->getOpcode() == ISD::SREM    || N->getOpcode() == ISD::UREM) &&
          "Unhandled Opcode in getDivRemArgList");
@@ -12060,12 +12073,15 @@ static TargetLowering::ArgListTy getDivRemArgList(
     Entry.isZExt = !isSigned;
     Args.push_back(Entry);
   }
 +  if (Subtarget->isTargetWindows() && Args.size() >= 2)
 +    std::swap(Args[0], Args[1]);
   return Args;
 }
 SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
   assert((Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
 -          Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI()) &&
 +          Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
 +          Subtarget->isTargetWindows()) &&
          "Register-based DivRem lowering only");
   unsigned Opcode = Op->getOpcode();
   assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
@@ -12079,13 +12095,17 @@ SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
   SDValue InChain = DAG.getEntryNode();
   TargetLowering::ArgListTy Args = getDivRemArgList(Op.getNode(),
 -                                                    DAG.getContext());
 +                                                    DAG.getContext(),
 +                                                    Subtarget);
   SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
                                          getPointerTy(DAG.getDataLayout()));
   Type *RetTy = (Type*)StructType::get(Ty, Ty, nullptr);
 +  if (Subtarget->isTargetWindows())
 +    InChain = WinDBZCheckDenominator(DAG, Op.getNode(), InChain);
 +
   SDLoc dl(Op);
   TargetLowering::CallLoweringInfo CLI(DAG);
   CLI.setDebugLoc(dl).setChain(InChain)
@@ -12119,11 +12139,15 @@ SDValue ARMTargetLowering::LowerREM(SDNode *N, SelectionDAG &DAG) const {
   RTLIB::Libcall LC = getDivRemLibcall(N, N->getValueType(0).getSimpleVT().
                                                              SimpleTy);
   SDValue InChain = DAG.getEntryNode();
 -  TargetLowering::ArgListTy Args = getDivRemArgList(N, DAG.getContext());
 +  TargetLowering::ArgListTy Args = getDivRemArgList(N, DAG.getContext(),
 +                                                    Subtarget);
   bool isSigned = N->getOpcode() == ISD::SREM;
   SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
                                          getPointerTy(DAG.getDataLayout()));
 +  if (Subtarget->isTargetWindows())
 +    InChain = WinDBZCheckDenominator(DAG, N, InChain);
 +
   // Lower call
   CallLoweringInfo CLI(DAG);
   CLI.setChain(InChain)
 diff --git a/test/CodeGen/ARM/Windows/dbzchk.ll b/test/CodeGen/ARM/Windows/dbzchk.ll
 index 599a7cf..c078e09 100644
 --- a/test/CodeGen/ARM/Windows/dbzchk.ll
 +++ b/test/CodeGen/ARM/Windows/dbzchk.ll
@@ -141,7 +141,7 @@ attributes #0 = { optsize }
 ; CHECK-CFG-ASM-NEXT: udf.w #249
 ; CHECK-CFG-ASM-LABEL: .LBB2_4:
 ; CHECK-CFG-ASM: bl __rt_udiv
 -; CHECK-CFG-ASM: pop.w {{{.*}}, r11, pc}
 +; CHECK-CFG-ASM: pop.w {r11, pc}
 ; RUN: llc -O0 -mtriple thumbv7--windows-itanium -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-WIN__DBZCHK
 diff --git a/test/CodeGen/ARM/divmod-eabi.ll b/test/CodeGen/ARM/divmod-eabi.ll
 index 1e4c8fc..ce5a1df 100644
 --- a/test/CodeGen/ARM/divmod-eabi.ll
 +++ b/test/CodeGen/ARM/divmod-eabi.ll
@@ -42,15 +42,13 @@ entry:
 ; DARWIN-DEFAULT: add [[sum:r[0-9]+]], r0, [[div]]
 ; DARWIN-O0: mov [[rem:r[0-9]+]], r0
 ; WINDOWS: __rt_sdiv
 -; WINDOWS-DEFAULT: mls [[rem:r[0-9]+]], r0,
 -; WINDOWS-DEFAULT: adds [[sum:r[0-9]+]], [[rem]], r0
 -; WINDOWS-O0: mov [[div:r[0-9]+]], r0
 -; WINDOWS-O0: mls [[rem:r[0-9]+]], [[div]],
 +; WINDOWS: __rt_sdiv
 +; WINDOWS-DEFAULT: add [[sum:r[0-9]+]], r1
 +; WINDOWS-O0: mov [[rem:r[0-9]+]], r1
   %rem8 = srem i32 %conv1, %conv
 ; EABI: __aeabi_idivmod
 ; DARWIN: __modsi3
 ; WINDOWS: __rt_sdiv
 -; WINDOWS: mls [[rem1:r[0-9]+]], r0,
   %add = add nsw i32 %rem, %div
   %add13 = add nsw i32 %add, %rem8
   %conv14 = trunc i32 %add13 to i16
@@ -60,9 +58,10 @@ entry:
 ; DARWIN-O0: add [[sum:r[0-9]+]], [[rem]], [[div]]
 ; DARWIN-O0: add [[res:r[0-9]+]], [[sum]], r0
 ; DARWIN: sxth r0, [[res]]
 -; WINDOWS-O0: adds [[sum:r[0-9]+]], [[rem]], [[div]]
 -; WINDOWS: add [[rem1]], [[sum]]
 -; WINDOWS: sxth [[res:r[0-9]+]], [[rem1]]
 +; WINDOWS-DEFAULT: adds [[sum1:r[0-9]+]], [[sum]], r1
 +; WINDOWS-O0: adds [[sum:r[0-9]+]], [[rem]],
 +; WINDOWS-O0: add [[sum1:r[0-9]+]], r1
 +; WINDOWS: sxth [[res:r[0-9]+]], [[sum1]]
   ret i16 %conv14
 }
@@ -84,22 +83,20 @@ entry:
 ; WINDOWS: __rt_sdiv
 ; WINDOWS: mov [[div:r[0-9]+]], r0
 ; WINDOWS: __rt_sdiv
 -; WINDOWS: mls [[rem:r[0-9]+]], r0,
 -; WINDOWS-DEFAULT: add [[div]], [[rem]]
 +; WINDOWS-DEFAULT: add [[div]], r1
   %rem1 = srem i32 %b, %a
 ; EABI: __aeabi_idivmod
 ; DARWIN: __modsi3
 ; WINDOWS: __rt_sdiv
 -; WINDOWS: mls [[rem1:r[0-9]+]], r0,
   %add = add nsw i32 %rem, %div
   %add2 = add nsw i32 %add, %rem1
 ; EABI: add r0{{.*}}r1
 ; DARWIN-DEFAULT: add r0, [[sum]], r0
 ; DARWIN-O0: add [[sum:r[0-9]+]], [[rem]], [[div]]
 ; DARWIN-O0: add [[res:r[0-9]+]], [[sum]], r0
 -; WINDOWS-DEFAULT: add [[rem1]], [[div]]
 +; WINDOWS-DEFAULT: adds r0, [[div]], r1
 ; WINDOWS-O0: adds [[sum:r[0-9]+]], [[rem]], [[div]]
 -; WINDOWS-O0: add [[rem1]], [[sum]]
 +; WINDOWS-O0: add [[sum]], r1
   ret i32 %add2
 }
@@ -119,22 +116,20 @@ entry:
 ; WINDOWS: __rt_udiv
 ; WINDOWS: mov [[div:r[0-9]+]], r0
 ; WINDOWS: __rt_udiv
 -; WINDOWS: mls [[rem:r[0-9]+]], r0,
 -; WINDOWS-DEFAULT: add [[div]], [[rem]]
 +; WINDOWS-DEFAULT: add [[div]], r1
   %rem1 = urem i32 %b, %a
 ; EABI: __aeabi_uidivmod
 ; DARWIN: __umodsi3
 ; WINDOWS: __rt_udiv
 -; WINDOWS: mls [[rem1:r[0-9]+]], r0,
   %add = add nuw i32 %rem, %div
   %add2 = add nuw i32 %add, %rem1
 ; EABI: add r0{{.*}}r1
 ; DARWIN-DEFAULT: add r0, [[sum]], r0
 ; DARWIN-O0: add [[sum:r[0-9]+]], [[rem]], [[div]]
 ; DARWIN-O0: add [[res:r[0-9]+]], [[sum]], r0
 -; WINDOWS-DEFAULT: add [[rem1]], [[div]]
 -; WINDOWS-O0: adds [[sum:r[0-9]+]], [[rem]], [[div]]
 -; WINDOWS-O0: add [[rem1]], [[sum]]
 +; WINDOWS-DEFAULT: adds [[sum:r[0-9]+]], [[div]], r1
 +; WINDOWS-O0: adds [[sum:r[0-9]+]],
 +; WINDOWS-O0: add [[sum]], r1
   ret i32 %add2
 }
@@ -154,14 +149,11 @@ entry:
 ; DARWIN: mov [[div2:r[0-9]+]], r1
 ; DARWIN: __moddi3
 ; WINDOWS: __rt_sdiv64
 -; WINDOWS: mov [[div1:r[0-9]+]], r0
 -; WINDOWS: mov [[div2:r[0-9]+]], r1
 -; WINDOWS: __moddi3
   %add = add nsw i64 %rem, %div
 ; DARWIN: adds r0{{.*}}[[div1]]
 ; DARWIN: adc r1{{.*}}[[div2]]
 -; WINDOWS: adds.w r0, r0, [[div1]]
 -; WINDOWS: adc.w r1, r1, [[div2]]
 +; WINDOWS: adds r0, r0, r2
 +; WINDOWS: adcs r1, r3
   ret i64 %add
 }
@@ -179,11 +171,10 @@ entry:
 ; WINDOWS: __rt_sdiv
 ; WINDOWS: mov [[div:r[0-9]+]], r0
 ; WINDOWS: __rt_sdiv
 -; WINDOWS: mls [[rem:r[0-9]+]], r0,
   %add = add nsw i16 %rem, %div
 ; EABI: add r0, r1
 ; DARWIN: add r0{{.*}}[[div1]]
 -; WINDOWS: add [[rem]], [[div]]
 +; WINDOWS: adds r0, r1, [[div]]
   ret i16 %add
 }
@@ -201,11 +192,10 @@ entry:
 ; WINDOWS: __rt_sdiv
 ; WINDOWS: mov [[div:r[0-9]+]], r0
 ; WINDOWS: __rt_sdiv
 -; WINDOWS: mls [[rem:r[0-9]+]], r0,
   %add = add nsw i32 %rem, %div
 ; EABI:	add	r0{{.*}}r1
 ; DARWIN: add r0{{.*}}[[sum]]
 -; WINDOWS: add [[rem]], [[div]]
 +; WINDOWS: adds r0, r1, [[div]]
   ret i32 %add
 }
@@ -221,7 +211,7 @@ entry:
 ; WINDOWS: __rt_sdiv
   ret i32 %rem
 ; EABI:	mov	r0, r1
 -; WINDOWS: mls r0, r0,
 +; WINDOWS: mov  r0, r1
 }
 define i32 @g3(i32 %a, i32 %b) {
@@ -235,16 +225,15 @@ entry:
 ; DARWIN: __modsi3
 ; DARWIN: mov [[sum:r[0-9]+]], r0
 ; WINDOWS: __rt_sdiv
 -; WINDOWS: mls [[rem:r[0-9]+]], r0,
 +; WINDOWS: mov [[rem:r[0-9]+]], r1
   %rem1 = srem i32 %b, %rem
 ; EABI: __aeabi_idivmod
 ; DARWIN: __modsi3
 ; WINDOWS: __rt_sdiv
 -; WINDOWS: mls [[rem1:r[0-9]+]], r0,
   %add = add nsw i32 %rem1, %rem
 ; EABI: add r0, r1, [[mod]]
 ; DARWIN: add r0{{.*}}[[sum]]
 -; WINDOWS: add [[rem1]], [[rem]]
 +; WINDOWS: adds r0, r1, [[rem]]
   ret i32 %add
 }
@@ -264,10 +253,9 @@ entry:
 ; EABI: __aeabi_idivmod
 ; DARWIN: __modsi3
 ; WINDOWS: __rt_sdiv
 -; WINDOWS: mls [[rem:r[0-9]+]], r0,
   %add = add nsw i32 %rem, %div
 ; EABI: add r0, r1, [[div]]
 ; DARWIN: add r0{{.*}}[[sum]]
 -; WINDOWS: add [[rem]], [[div]]
 +; WINDOWS: adds r0, r1, [[div]]
   ret i32 %add
 }
 -- 
 2.7.4
@@ -1,250 +0,0 @@
 From a6c33deef382981590bd9298b492b612bcbae521 Mon Sep 17 00:00:00 2001
 From: Saleem Abdulrasool <compnerd@compnerd.org>
 Date: Thu, 27 Oct 2016 16:59:22 +0000
 Subject: [PATCH 8/9] ARM: ensure that the Windows DBZ check is in range
 The Windows ARM target expects the compiler to emit a division-by-zero check.
 The check would use the form of:
    cmp r?, #0
    cbz .Ltrap
    b .Lbody
  .Lbody:
    ...
  .Ltrap:
    udf #249 @ __brkdiv0
 This works great most of the time.  However, if the body of the function is
 greater than 127 bytes, the branch target limitation of cbz becomes an issue.
 This occurs in the unoptimized code generation cases sometimes (like in
 compiler-rt).
 Since this is a matter of correctness, possibly pay a small penalty instead.  We
 now form this slightly differently:
    cbnz .Lbody
    udf #249 @ __brkdiv0
  .Lbody:
    ...
 The positive case is through the branch instead of being the next instruction.
 However, because of the basic block layout, the negated branch is going to be
 a short distance always (2 bytes away, after the inserted __brkdiv0).
 The new t__brkdiv0 instruction is required to explicitly mark the instruction as
 a terminator as the generic UDF instruction is not a terminator.
 Addresses PR30532!
 Cherry-picked from SVN trunk commit 285312, git mirror commit
 b5143b06a12b5.
 ---
 lib/Target/ARM/ARMISelLowering.cpp         | 11 +++------
 lib/Target/ARM/ARMInstrThumb.td            |  7 ++++++
 test/CodeGen/ARM/Windows/dbzchk.ll         | 38 +++++++++++-------------------
 test/CodeGen/ARM/Windows/division-range.ll | 15 ++++++++++++
 test/CodeGen/ARM/Windows/division.ll       | 20 +++++++---------
 5 files changed, 47 insertions(+), 44 deletions(-)
 create mode 100644 test/CodeGen/ARM/Windows/division-range.ll
 diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
 index 8db9f54..f7b09fa 100644
 --- a/lib/Target/ARM/ARMISelLowering.cpp
 +++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -8215,16 +8215,11 @@ ARMTargetLowering::EmitLowered__dbzchk(MachineInstr &MI,
                  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
   ContBB->transferSuccessorsAndUpdatePHIs(MBB);
 -  MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
 -  MF->push_back(TrapBB);
 -  BuildMI(TrapBB, DL, TII->get(ARM::t2UDF)).addImm(249);
 -  MBB->addSuccessor(TrapBB);
 -
 -  BuildMI(*MBB, MI, DL, TII->get(ARM::tCBZ))
 +  BuildMI(*MBB, MI, DL, TII->get(ARM::tCBNZ))
       .addReg(MI.getOperand(0).getReg())
 -      .addMBB(TrapBB);
 -  AddDefaultPred(BuildMI(*MBB, MI, DL, TII->get(ARM::t2B)).addMBB(ContBB));
 +      .addMBB(ContBB);
   MBB->addSuccessor(ContBB);
 +  BuildMI(*MBB, MI, DL, TII->get(ARM::t__brkdiv0));
   MI.eraseFromParent();
   return ContBB;
 diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
 index 93a174f..6c759a1 100644
 --- a/lib/Target/ARM/ARMInstrThumb.td
 +++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -1259,6 +1259,13 @@ def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8",
   let Inst{7-0} = imm8;
 }
 +def t__brkdiv0 : TI<(outs), (ins), IIC_Br, "__brkdiv0",
 +                    [(int_arm_undefined 249)]>, Encoding16,
 +    Requires<[IsThumb, IsWindows]> {
 +  let Inst = 0xdef9;
 +  let isTerminator = 1;
 +}
 +
 // Zero-extend byte
 def tUXTB :                     // A8.6.262
   T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
 diff --git a/test/CodeGen/ARM/Windows/dbzchk.ll b/test/CodeGen/ARM/Windows/dbzchk.ll
 index c078e09..af23cb2 100644
 --- a/test/CodeGen/ARM/Windows/dbzchk.ll
 +++ b/test/CodeGen/ARM/Windows/dbzchk.ll
@@ -33,15 +33,12 @@ return:
 }
 ; CHECK-DIV-DAG: BB#0
 -; CHECK-DIV-DAG: Successors according to CFG: BB#5({{.*}}) BB#4
 +; CHECK-DIV-DAG: Successors according to CFG: BB#1({{.*}}) BB#2
 ; CHECK-DIV-DAG: BB#1
 ; CHECK-DIV-DAG: Successors according to CFG: BB#3
 ; CHECK-DIV-DAG: BB#2
 ; CHECK-DIV-DAG: Successors according to CFG: BB#3
 ; CHECK-DIV-DAG: BB#3
 -; CHECK-DIV-DAG: BB#4
 -; CHECK-DIV-DAG: Successors according to CFG: BB#1({{.*}}) BB#2
 -; CHECK-DIV-DAG: BB#5
 ; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-MOD
@@ -72,11 +69,10 @@ return:
 ; CHECK-MOD-DAG: BB#0
 ; CHECK-MOD-DAG: Successors according to CFG: BB#2({{.*}}) BB#1
 ; CHECK-MOD-DAG: BB#1
 -; CHECK-MOD-DAG: Successors according to CFG: BB#4({{.*}}) BB#3
 -; CHECK-MOD-DAG: BB#2
 +; CHECK-MOD-DAG: Successors according to CFG: BB#3
 ; CHECK-MOD-DAG: BB#3
 ; CHECK-MOD-DAG: Successors according to CFG: BB#2
 -; CHECK-MOD-DAG: BB#4
 +; CHECK-MOD-DAG: BB#2
 ; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -filetype asm -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-CFG
 ; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-CFG-ASM
@@ -123,25 +119,19 @@ attributes #0 = { optsize }
 ; CHECK-CFG-DAG: t2B <BB#3>
 ; CHECK-CFG-DAG: BB#2
 -; CHECK-CFG-DAG: tCBZ %vreg{{[0-9]}}, <BB#5>
 -; CHECK-CFG-DAG: t2B <BB#4>
 +; CHECK-CFG-DAG: tCBNZ %vreg{{[0-9]}}, <BB#4>
 +; CHECK-CFG-DAG: t__brkdiv0
 ; CHECK-CFG-DAG: BB#4
 ; CHECK-CFG-DAG: BB#3
 ; CHECK-CFG-DAG: tBX_RET
 -; CHECK-CFG-DAG: BB#5
 -; CHECK-CFG-DAG: t2UDF 249
 -
 ; CHECK-CFG-ASM-LABEL: h:
 -; CHECK-CFG-ASM: cbz r{{[0-9]}}, .LBB2_2
 -; CHECK-CFG-ASM: b .LBB2_4
 +; CHECK-CFG-ASM: cbnz r{{[0-9]}}, .LBB2_2
 +; CHECK-CFG-ASM: __brkdiv0
 ; CHECK-CFG-ASM-LABEL: .LBB2_2:
 -; CHECK-CFG-ASM-NEXT: udf.w #249
 -; CHECK-CFG-ASM-LABEL: .LBB2_4:
 ; CHECK-CFG-ASM: bl __rt_udiv
 -; CHECK-CFG-ASM: pop.w {r11, pc}
 ; RUN: llc -O0 -mtriple thumbv7--windows-itanium -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-WIN__DBZCHK
@@ -182,11 +172,11 @@ return:
 }
 ; CHECK-WIN__DBZCHK-LABEL: j:
 -; CHECK-WIN__DBZCHK: cbz r{{[0-7]}}, .LBB
 -; CHECK-WIN__DBZCHK-NOT: cbz r8, .LBB
 -; CHECK-WIN__DBZCHK-NOT: cbz r9, .LBB
 -; CHECK-WIN__DBZCHK-NOT: cbz r10, .LBB
 -; CHECK-WIN__DBZCHK-NOT: cbz r11, .LBB
 -; CHECK-WIN__DBZCHK-NOT: cbz ip, .LBB
 -; CHECK-WIN__DBZCHK-NOT: cbz lr, .LBB
 +; CHECK-WIN__DBZCHK: cbnz r{{[0-7]}}, .LBB
 +; CHECK-WIN__DBZCHK-NOT: cbnz r8, .LBB
 +; CHECK-WIN__DBZCHK-NOT: cbnz r9, .LBB
 +; CHECK-WIN__DBZCHK-NOT: cbnz r10, .LBB
 +; CHECK-WIN__DBZCHK-NOT: cbnz r11, .LBB
 +; CHECK-WIN__DBZCHK-NOT: cbnz ip, .LBB
 +; CHECK-WIN__DBZCHK-NOT: cbnz lr, .LBB
 diff --git a/test/CodeGen/ARM/Windows/division-range.ll b/test/CodeGen/ARM/Windows/division-range.ll
 new file mode 100644
 index 0000000..9b1920c
 --- /dev/null
 +++ b/test/CodeGen/ARM/Windows/division-range.ll
@@ -0,0 +1,15 @@
 +; RUN: llc -O0 -mtriple thumbv7--windows-itanium -filetype obj -o - %s | llvm-objdump -disassemble - | FileCheck %s
 +
 +declare i32 @llvm.arm.space(i32, i32)
 +
 +define arm_aapcs_vfpcc i32 @f(i32 %n, i32 %d) local_unnamed_addr {
 +entry:
 +  %div = sdiv i32 %n, %d
 +  call i32 @llvm.arm.space(i32 128, i32 undef)
 +  ret i32 %div
 +}
 +
 +; CHECK: cbnz r1, #0
 +; CHECK: __brkdiv0
 +; CHECK: bl
 +
 diff --git a/test/CodeGen/ARM/Windows/division.ll b/test/CodeGen/ARM/Windows/division.ll
 index f4704ea..b149cb0 100644
 --- a/test/CodeGen/ARM/Windows/division.ll
 +++ b/test/CodeGen/ARM/Windows/division.ll
@@ -8,9 +8,8 @@ entry:
 }
 ; CHECK-LABEL: sdiv32:
 -; CHECK: cbz r0
 -; CHECK: b
 -; CHECK: udf.w #249
 +; CHECK: cbnz r0
 +; CHECK: __brkdiv0
 ; CHECK: bl __rt_sdiv
 define arm_aapcs_vfpcc i32 @udiv32(i32 %divisor, i32 %divident) {
@@ -20,9 +19,8 @@ entry:
 }
 ; CHECK-LABEL: udiv32:
 -; CHECK: cbz r0
 -; CHECK: b
 -; CHECK: udf.w #249
 +; CHECK: cbnz r0
 +; CHECK: __brkdiv0
 ; CHECK: bl __rt_udiv
 define arm_aapcs_vfpcc i64 @sdiv64(i64 %divisor, i64 %divident) {
@@ -33,9 +31,8 @@ entry:
 ; CHECK-LABEL: sdiv64:
 ; CHECK: orr.w r4, r0, r1
 -; CHECK-NEXT: cbz r4
 -; CHECK: b
 -; CHECK: udf.w #249
 +; CHECK-NEXT: cbnz r4
 +; CHECK: __brkdiv0
 ; CHECK: bl __rt_sdiv64
 define arm_aapcs_vfpcc i64 @udiv64(i64 %divisor, i64 %divident) {
@@ -46,8 +43,7 @@ entry:
 ; CHECK-LABEL: udiv64:
 ; CHECK: orr.w r4, r0, r1
 -; CHECK-NEXT: cbz r4
 -; CHECK: b
 -; CHECK: udf.w #249
 +; CHECK-NEXT: cbnz r4
 +; CHECK: __brkdiv0
 ; CHECK: bl __rt_udiv64
 -- 
 2.7.4
@@ -1,186 +0,0 @@
 From 20692f7f7548e98523818db6d83ca66e3ae0dedc Mon Sep 17 00:00:00 2001
 From: Saleem Abdulrasool <compnerd@compnerd.org>
 Date: Mon, 31 Oct 2016 22:12:37 +0000
 Subject: [PATCH 9/9] CodeGen: further loosen -O0 CG for WoA division
 Generate the slowest possible codepath for noopt CodeGen.  Even trying to be
 clever with the negated jump can cause out-of-range jumps.  Use a wide branch
 instead. Although the code is modelled simplistically, the later optimizations
 would recombine the branching into `cbz` if possible.  This re-enables the
 previous optimization as well as hopefully gives us working code in all cases.
 Addresses PR30356!
 Cherry-picked from SVN trunk commit 285649, git mirror commit
 f185e91e2bc8.
 ---
 lib/Target/ARM/ARMISelLowering.cpp         | 18 ++++++++++++-----
 test/CodeGen/ARM/Windows/dbzchk.ll         | 31 ++++++++++++++++--------------
 test/CodeGen/ARM/Windows/division-range.ll |  4 ++--
 test/CodeGen/ARM/Windows/division.ll       | 20 +++++++++----------
 4 files changed, 42 insertions(+), 31 deletions(-)
 diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
 index f7b09fa..6d4e6d7 100644
 --- a/lib/Target/ARM/ARMISelLowering.cpp
 +++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -8214,12 +8214,20 @@ ARMTargetLowering::EmitLowered__dbzchk(MachineInstr &MI,
   ContBB->splice(ContBB->begin(), MBB,
                  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
   ContBB->transferSuccessorsAndUpdatePHIs(MBB);
 -
 -  BuildMI(*MBB, MI, DL, TII->get(ARM::tCBNZ))
 -      .addReg(MI.getOperand(0).getReg())
 -      .addMBB(ContBB);
   MBB->addSuccessor(ContBB);
 -  BuildMI(*MBB, MI, DL, TII->get(ARM::t__brkdiv0));
 +
 +  MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
 +  BuildMI(TrapBB, DL, TII->get(ARM::t__brkdiv0));
 +  MF->push_back(TrapBB);
 +  MBB->addSuccessor(TrapBB);
 +
 +  AddDefaultPred(BuildMI(*MBB, MI, DL, TII->get(ARM::tCMPi8))
 +                     .addReg(MI.getOperand(0).getReg())
 +                     .addImm(0));
 +  BuildMI(*MBB, MI, DL, TII->get(ARM::t2Bcc))
 +      .addMBB(TrapBB)
 +      .addImm(ARMCC::EQ)
 +      .addReg(ARM::CPSR);
   MI.eraseFromParent();
   return ContBB;
 diff --git a/test/CodeGen/ARM/Windows/dbzchk.ll b/test/CodeGen/ARM/Windows/dbzchk.ll
 index af23cb2..aea3799 100644
 --- a/test/CodeGen/ARM/Windows/dbzchk.ll
 +++ b/test/CodeGen/ARM/Windows/dbzchk.ll
@@ -75,7 +75,7 @@ return:
 ; CHECK-MOD-DAG: BB#2
 ; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -filetype asm -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-CFG
 -; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-CFG-ASM
 +; RUN: llc -mtriple thumbv7--windows-itanium -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-CFG-ASM
 ; unsigned c;
 ; extern unsigned long g(void);
@@ -119,21 +119,24 @@ attributes #0 = { optsize }
 ; CHECK-CFG-DAG: t2B <BB#3>
 ; CHECK-CFG-DAG: BB#2
 -; CHECK-CFG-DAG: tCBNZ %vreg{{[0-9]}}, <BB#4>
 -; CHECK-CFG-DAG: t__brkdiv0
 +; CHECK-CFG-DAG: tCMPi8 %vreg{{[0-9]}}, 0
 +; CHECK-CFG-DAG: t2Bcc <BB#5>
 ; CHECK-CFG-DAG: BB#4
 ; CHECK-CFG-DAG: BB#3
 ; CHECK-CFG-DAG: tBX_RET
 +; CHECK-CFG-DAG: BB#5
 +; CHECK-CFG-DAG: t__brkdiv0
 +
 ; CHECK-CFG-ASM-LABEL: h:
 -; CHECK-CFG-ASM: cbnz r{{[0-9]}}, .LBB2_2
 -; CHECK-CFG-ASM: __brkdiv0
 -; CHECK-CFG-ASM-LABEL: .LBB2_2:
 +; CHECK-CFG-ASM: cbz r{{[0-9]}}, .LBB2_4
 ; CHECK-CFG-ASM: bl __rt_udiv
 +; CHECK-CFG-ASM-LABEL: .LBB2_4:
 +; CHECK-CFG-ASM: __brkdiv0
 -; RUN: llc -O0 -mtriple thumbv7--windows-itanium -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-WIN__DBZCHK
 +; RUN: llc -O1 -mtriple thumbv7--windows-itanium -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-WIN__DBZCHK
 ; long k(void);
 ; int l(void);
@@ -172,11 +175,11 @@ return:
 }
 ; CHECK-WIN__DBZCHK-LABEL: j:
 -; CHECK-WIN__DBZCHK: cbnz r{{[0-7]}}, .LBB
 -; CHECK-WIN__DBZCHK-NOT: cbnz r8, .LBB
 -; CHECK-WIN__DBZCHK-NOT: cbnz r9, .LBB
 -; CHECK-WIN__DBZCHK-NOT: cbnz r10, .LBB
 -; CHECK-WIN__DBZCHK-NOT: cbnz r11, .LBB
 -; CHECK-WIN__DBZCHK-NOT: cbnz ip, .LBB
 -; CHECK-WIN__DBZCHK-NOT: cbnz lr, .LBB
 +; CHECK-WIN__DBZCHK: cbz r{{[0-7]}}, .LBB
 +; CHECK-WIN__DBZCHK-NOT: cbz r8, .LBB
 +; CHECK-WIN__DBZCHK-NOT: cbz r9, .LBB
 +; CHECK-WIN__DBZCHK-NOT: cbz r10, .LBB
 +; CHECK-WIN__DBZCHK-NOT: cbz r11, .LBB
 +; CHECK-WIN__DBZCHK-NOT: cbz ip, .LBB
 +; CHECK-WIN__DBZCHK-NOT: cbz lr, .LBB
 diff --git a/test/CodeGen/ARM/Windows/division-range.ll b/test/CodeGen/ARM/Windows/division-range.ll
 index 9b1920c..b14339e 100644
 --- a/test/CodeGen/ARM/Windows/division-range.ll
 +++ b/test/CodeGen/ARM/Windows/division-range.ll
@@ -9,7 +9,7 @@ entry:
   ret i32 %div
 }
 -; CHECK: cbnz r1, #0
 -; CHECK: __brkdiv0
 +; CHECK: cmp r1, #0
 +; CHECK: beq #
 ; CHECK: bl
 diff --git a/test/CodeGen/ARM/Windows/division.ll b/test/CodeGen/ARM/Windows/division.ll
 index b149cb0..10f86b0 100644
 --- a/test/CodeGen/ARM/Windows/division.ll
 +++ b/test/CodeGen/ARM/Windows/division.ll
@@ -8,9 +8,9 @@ entry:
 }
 ; CHECK-LABEL: sdiv32:
 -; CHECK: cbnz r0
 -; CHECK: __brkdiv0
 +; CHECK: cbz r0
 ; CHECK: bl __rt_sdiv
 +; CHECK: __brkdiv0
 define arm_aapcs_vfpcc i32 @udiv32(i32 %divisor, i32 %divident) {
 entry:
@@ -19,9 +19,9 @@ entry:
 }
 ; CHECK-LABEL: udiv32:
 -; CHECK: cbnz r0
 -; CHECK: __brkdiv0
 +; CHECK: cbz r0
 ; CHECK: bl __rt_udiv
 +; CHECK: __brkdiv0
 define arm_aapcs_vfpcc i64 @sdiv64(i64 %divisor, i64 %divident) {
 entry:
@@ -30,10 +30,10 @@ entry:
 }
 ; CHECK-LABEL: sdiv64:
 -; CHECK: orr.w r4, r0, r1
 -; CHECK-NEXT: cbnz r4
 -; CHECK: __brkdiv0
 +; CHECK: orrs.w r4, r0, r1
 +; CHECK-NEXT: beq
 ; CHECK: bl __rt_sdiv64
 +; CHECK: __brkdiv0
 define arm_aapcs_vfpcc i64 @udiv64(i64 %divisor, i64 %divident) {
 entry:
@@ -42,8 +42,8 @@ entry:
 }
 ; CHECK-LABEL: udiv64:
 -; CHECK: orr.w r4, r0, r1
 -; CHECK-NEXT: cbnz r4
 -; CHECK: __brkdiv0
 +; CHECK: orrs.w r4, r0, r1
 +; CHECK-NEXT: beq
 ; CHECK: bl __rt_udiv64
 +; CHECK: __brkdiv0
 -- 
 2.7.4