Update to the LLVM 4.0 release branch
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Martin Storsjö authored and Martin Storsjo committed
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@@ -1,133 +0,0 @@
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From 9ce71bff387ce9e30adddf72a29874bbb058dd5a Mon Sep 17 00:00:00 2001
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From: Sam Parker <sam.parker@arm.com>
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Date: Mon, 25 Jul 2016 09:20:20 +0000
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Subject: [PATCH 2/3] [ARM] Enable ISel of SMMLS for ARM and Thumb2
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Use ISelDAGToDAG to recognise the SMMLS instruction pattern.
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Differential Revision: https://reviews.llvm.org/D22562
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Cherry-picked from SVN trunk commit 276624, git mirror commit
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161eae5670.
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---
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lib/Target/ARM/ARMISelDAGToDAG.cpp | 30 ++++++++++++++++++++++++++++++
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lib/Target/ARM/ARMInstrThumb2.td | 9 ++++-----
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test/CodeGen/ARM/smml.ll | 36 ++++++++++++++++++++++++++++++++++--
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3 files changed, 68 insertions(+), 7 deletions(-)
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diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
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index 20db3d3..96cb691 100644
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--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
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+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
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@@ -3037,6 +3037,36 @@ void ARMDAGToDAGISel::Select(SDNode *N) {
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return;
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}
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}
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+ case ARMISD::SUBE: {
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+ if (!Subtarget->hasV6Ops())
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+ break;
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+ // Look for a pattern to match SMMLS
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+ // (sube a, (smul_loHi a, b), (subc 0, (smul_LOhi(a, b))))
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+ if (N->getOperand(1).getOpcode() != ISD::SMUL_LOHI ||
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+ N->getOperand(2).getOpcode() != ARMISD::SUBC)
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+ break;
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+
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+ if (Subtarget->isThumb())
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+ assert(Subtarget->hasThumb2() &&
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+ "This pattern should not be generated for Thumb");
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+
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+ SDValue SmulLoHi = N->getOperand(1);
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+ SDValue Subc = N->getOperand(2);
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+ auto *Zero = dyn_cast<ConstantSDNode>(Subc.getOperand(0));
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+
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+ if (!Zero || Zero->getZExtValue() != 0 ||
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+ Subc.getOperand(1) != SmulLoHi.getValue(0) ||
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+ N->getOperand(1) != SmulLoHi.getValue(1) ||
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+ N->getOperand(2) != Subc.getValue(1))
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+ break;
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+
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+ unsigned Opc = Subtarget->isThumb2() ? ARM::t2SMMLS : ARM::SMMLS;
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+ SDValue Ops[] = { SmulLoHi.getOperand(0), SmulLoHi.getOperand(1),
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+ N->getOperand(0), getAL(CurDAG, dl),
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+ CurDAG->getRegister(0, MVT::i32) };
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+ ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops));
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+ return;
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+ }
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case ISD::LOAD: {
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if (Subtarget->isThumb() && Subtarget->hasThumb2()) {
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if (tryT2IndexedLoad(N))
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diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
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index 64f5dad..599b552 100644
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--- a/lib/Target/ARM/ARMInstrThumb2.td
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+++ b/lib/Target/ARM/ARMInstrThumb2.td
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@@ -2606,12 +2606,11 @@ class T2FourRegSMMLA<bits<3> op22_20, bits<4> op7_4, string opc,
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let Inst{7-4} = op7_4;
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}
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-def t2SMMLA : T2FourRegSMMLA<0b101, 0b0000, "smmla",
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+def t2SMMLA : T2FourRegSMMLA<0b101, 0b0000, "smmla",
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[(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>;
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-def t2SMMLAR: T2FourRegSMMLA<0b101, 0b0001, "smmlar", []>;
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-def t2SMMLS: T2FourRegSMMLA<0b110, 0b0000, "smmls",
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- [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>;
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-def t2SMMLSR:T2FourRegSMMLA<0b110, 0b0001, "smmlsr", []>;
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+def t2SMMLAR: T2FourRegSMMLA<0b101, 0b0001, "smmlar", []>;
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+def t2SMMLS: T2FourRegSMMLA<0b110, 0b0000, "smmls", []>;
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+def t2SMMLSR: T2FourRegSMMLA<0b110, 0b0001, "smmlsr", []>;
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class T2ThreeRegSMUL<bits<3> op22_20, bits<2> op5_4, string opc,
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list<dag> pattern>
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diff --git a/test/CodeGen/ARM/smml.ll b/test/CodeGen/ARM/smml.ll
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index fc73eb7..807445f 100644
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--- a/test/CodeGen/ARM/smml.ll
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+++ b/test/CodeGen/ARM/smml.ll
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@@ -1,8 +1,20 @@
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-; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
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+; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=CHECK
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+; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V6
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+; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V7
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+; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s -check-prefix=CHECK-THUMB
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+; RUN: llc -mtriple=thumbv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK-THUMB
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+; RUN: llc -mtriple=thumbv6t2-eabi %s -o - | FileCheck %s -check-prefix=CHECK-THUMBV6T2
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+; RUN: llc -mtriple=thumbv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK-THUMBV7
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-define i32 @f(i32 %a, i32 %b, i32 %c) nounwind readnone ssp {
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+define i32 @Test0(i32 %a, i32 %b, i32 %c) nounwind readnone ssp {
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entry:
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+; CHECK-LABEL: Test0
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; CHECK-NOT: smmls
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+; CHECK-V6-NOT: smmls
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+; CHECK-V7-NOT: smmls
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+; CHECK_THUMB-NOT: smmls
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+; CHECK-THUMBV6T2-NOT: smmls
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+; CHECK-THUMBV7-NOT: smmls
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%conv4 = zext i32 %a to i64
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%conv1 = sext i32 %b to i64
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%conv2 = sext i32 %c to i64
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@@ -12,3 +24,23 @@ entry:
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%conv3 = trunc i64 %sub to i32
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ret i32 %conv3
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}
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+
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+define i32 @Test1(i32 %a, i32 %b, i32 %c) {
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+;CHECK-LABEL: Test1
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+;CHECK-NOT: smmls
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+;CHECK-THUMB-NOT: smmls
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+;CHECK-V6: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
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+;CHECK-V7: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
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+;CHECK-THUMBV6T2: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
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+;CHECK-THUMBV7: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
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+entry:
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+ %conv = sext i32 %b to i64
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+ %conv1 = sext i32 %c to i64
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+ %mul = mul nsw i64 %conv1, %conv
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+ %conv26 = zext i32 %a to i64
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+ %shl = shl nuw i64 %conv26, 32
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+ %sub = sub nsw i64 %shl, %mul
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+ %shr7 = lshr i64 %sub, 32
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+ %conv3 = trunc i64 %shr7 to i32
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+ ret i32 %conv3
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+}
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--
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2.7.4
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